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Preliminary
HD66787
528-channel, One-chip Driver with 262,144-color Display RAM and Power Supply Circuit for Low-temperature Poli-Si TFT (LTPS-TFT) Panels with Incorporated Gate Drivers
REJxxxxxxx-xxxx Rev.0.22 10 June, 2003
Description ......................................................................................................... 5 Features ......................................................................................................... 6
Block Diagram .................................................................................................... 7 Pin Functions ...................................................................................................... 8 PAD Arrangement............................................................................................... 15 PAD Coordinate.................................................................................................. 16 BUMP Arrangements (T.B.D.) ........................................................................... 18 Block Function.................................................................................................... 19
1. System Interface ............................................................................................................... 19 2. External Display Interface ................................................................................................ 20 3. Bit Operations ................................................................................................................... 20 4. Address Counter (AC) ...................................................................................................... 20 5. Graphics RAM (GRAM) .................................................................................................. 20 7. Timing Generator.............................................................................................................. 20 8. Oscillation Circuit (OSC) ................................................................................................. 21 9. LCD Driver Circuit........................................................................................................... 21 10.LCD Drive Power Supply Circuit..................................................................................... 21
GRAM Address MAP......................................................................................... 22 Instructions ......................................................................................................... 29
Outline ................................................................................................................................... 29 Instruction Descriptions ......................................................................................................... 30 Index ...................................................................................................................................... 30 Status Read ............................................................................................................................ 31 Start Oscillation (R00h) ......................................................................................................... 31
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HD66787
Preliminary
Driver Output Control (R01h)................................................................................................ 31 LCD Driving Waveform Control (R02h)............................................................................... 33 Entry Mode (R03h) Compare Register 1 (R04h) Compare Register 2 (R05h) ..................... 34 Display Control 1 (R07h)....................................................................................................... 36 Display Control 2 (R08h)....................................................................................................... 38 Frame Cycle Control (R0Bh)................................................................................................. 40 External Display Interface Control (R0Ch) ........................................................................... 43 LTPS Interface Control (R0Dh)............................................................................................. 47 Power Control 1 (R10h) Power Control 2 (R11h) ................................................................. 51 Power Control 3 (R12h) Power Control 4 (R13h) ................................................................. 54 RAM Address Set (R21h)...................................................................................................... 56 Write Data to GRAM (R22h)................................................................................................. 57 RAM Access through RGB-I/F and System I/F..................................................................... 62 Read Data Read from GRAM (R22h).................................................................................... 63 RAM Write Data Mask (R23h) RAM Write Data Mask (R24h) ........................................... 66 Control (R30h to R39h)....................................................................................................... 67 Vertical Scroll Control (R41h)............................................................................................... 68 1st-Screen Drive Position (R42h) 2nd-Screen Drive Position (R43h)................................... 68 Horizontal RAM Address Position (R44h) Vertical RAM Address Position (R45h) ............ 69
Instruction List .................................................................................................... 70 Reset Function .................................................................................................... 71 Interface Specifications....................................................................................... 73 System Interface.................................................................................................. 75
80-system 18-bit interface...................................................................................................... 76 80-system 16-bit interface...................................................................................................... 77 80-system 9-bit interface........................................................................................................ 78 Data transmission synchronizing in 9-bit bus interface mode................................................ 79 80-system 8-bit interface........................................................................................................ 79 Data transmission synchronization in 8-bit bus interface mode............................................. 81 Serial Peripheral interface (SPI) ............................................................................................ 82
VSYNC Interface................................................................................................ 85
Conditions on using VSYNC interface .................................................................................. 87
External Display Interface .................................................................................. 89
RGB interface ........................................................................................................................ 89 VLD and ENABLE signals.................................................................................................... 90 RGB interface timing ............................................................................................................. 90 Moving picture display .......................................................................................................... 92 RAM access through system interface in RGB-I/F mode ...................................................... 92 6-bit RGB interface................................................................................................................ 93 Data transmission synchronization in 6-bit RGB interface mode .......................................... 93 16-bit RGB interface.............................................................................................................. 94 18-bit RGB interface.............................................................................................................. 95
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HD66787
Preliminary
Conditions on using external display interface ...................................................................... 96
Timing Interfacing with Liquid Crystal Panel Signals ....................................... 98
Register settings..................................................................................................................... 102
Low-temperature poli-Si TFT Panel Control...................................................... 104 High-Speed Burst RAM Write Function ............................................................ 106
Conditions on using high-speed RAM write mode ................................................................ 107 High-Speed RAM Write with Window Address Function..................................................... 108
Window Address Function ................................................................................. 110 Graphics Operation Function .............................................................................. 111
Graphics Operation ................................................................................................................ 111 Write-data Mask Function ..................................................................................................... 112 Graphics Operation Processing Examples ............................................................................. 112
-Correction Function ......................................................................................... 116
Configuration of Grayscale Amplifier ................................................................................... 117 -Correction Register ............................................................................................................. 119 Ladder resistors and 8-to-1 selector ....................................................................................... 120 Variable resistor..................................................................................................................... 120 Relationship between RAM data and output level................................................................. 126
8-color Display Mode ......................................................................................... 127 System Configuration ......................................................................................... 129 Configuration of Power Generation Circuit........................................................ 130 Specification of External Elements Connected to HD66787 Power Supply ...... 131 Instruction Setting Flow...................................................................................... 132 Power Supply Setting Flow ................................................................................ 134 Pattern Diagram for Voltage Setting................................................................... 135 Oscillation Circuit............................................................................................... 136 n-raster-row inversion AC drive ......................................................................... 137 AC Timing ......................................................................................................... 138 Frame-Frequency Adjustment Function ............................................................. 139
Relationship between Liquid Crystal Drive Duty and Frame Frequency .............................. 139
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HD66787
Preliminary
Screen-split Display Function ............................................................................ 140
Conditions on Setting the 1st/2nd Screen Drive Position Register ........................................ 141
Absolute Maximum Values ................................................................................ 143 Electric Characteristics (T.B.D.)......................................................................... 144
DC Characteristics ................................................................................................................. 144 AC Characteristics ................................................................................................................. 145 80-system Bus Interface Timing Characteristics.................................................................... 145 Serial Peripheral Interface Timing Characteristics ................................................................ 148 Reset Timing Characteristics (VCC = 1.8 to 3.7 V) ................................................................ 149 RGB interface timing characteristics ..................................................................................... 150 Liquid crystal driver output characteristics............................................................................ 152 Electrical Characteristics Notes ............................................................................................. 152 Load circuits for measuring AC characteristics ..................................................................... 155 80-system Bus Operation ....................................................................................................... 155 Clock Synchronized Serial Interface Operation..................................................................... 156 RESET Operation .................................................................................................................. 156 RGB I/F Operation................................................................................................................. 157 Liquid Crystal Driver Output................................................................................................. 157
Rev.0.22, May.23.2003, page 4 of 159
HD66787
Preliminary
Description
The HD66787 handles 262,144 TFT colors and can drive a TFT color liquid crystal display of 176RGB x 240 dots with an incorporated RAM compliant to a graphics display of 176 RGB x 240 dots at maximum, a 528-channel source driver, and a power supply circuit. The HD66787 generates signals to control panel-integrated gate circuit to drive a TFT panel with incorporated gate driver with a single chip. The HD66787's bit-operation functions, 8/9/16/18-bit high-speed bus interface, and high-speed RAM-write functions enable efficient transfer of data and high-speed data update on a graphics RAM. The HD66787 incorporates 6/16/18-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, and PD 17 to 0) and VSYNC interface (system interface + VSYNC) as an interface for moving picture display. With a window address function that facilitates the moving picture display in an arbitrary area and simultaneous display of moving pictures and the contents of the internal RAM, the HD66787 enables moving picture display not constrained by the still picture area. Accordingly, the data transmission is reduced to minimum, thereby saving power consumed by a system as a whole when displaying moving pictures. The HD66787 supports power-saving operation up to the power supply voltage of 2.4V with a voltage follower circuit that generate voltage to drive liquid crystal. The HD66787 also incorporates 8-color display and standby functions that allow precise power control by software. These features make this LSI the ideal solution for any medium or small sized portable battery-driven products such as digital cellular phones supporting WWW browsers or small PDA, where long battery life and board size are major concern.
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HD66787
Preliminary
Features
* * * * Liquid crystal controller/driver for 262,144 TFT-color 176RGB x 240-dot graphics display Control signal for a low-temperature poly-Si TFT (LTPS-TFT) panel with incorporated gate circuit Single chip solution for gate-less display panels System interface - 8-/9-/16-/18-bit high-speed bus interface - Serial Peripheral Interface (SPI) - 8-bit transmission x 3 times (262k/65k color modes) Interface for moving picture display - 6-/16-/18-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, PD17-0) - VSYNC interface (System interface + VSYNC) High-speed burst RAM write function Window address function to write data to the rectangular area of RAM specified by the window address - Interface to facilitate moving picture display in an arbitrary area - Reduce data transmission by transmitting only the data for the moving picture display area - Simultaneous display of moving pictures and the contents of the internal RAM Bit unit operations for processing graphics - Write data mask function by bit - Logical operation and conditional rewrite by pixel Functions for controlling abundant color displays - Simultaneous availability of 262,144 colors with -correction function - Line-unit vertical scrolling Low-power architecture: features for low-power operation - Vcc = 2.4 ~ 3.3 V (internal logic power supply) - IOVcc = 1.8 ~ 3.3 V (interface I/O power supply) - Vci = 2.5 ~ 3.3 V (analogue power supply) - DDVDH = 4.5 ~ 5.5 V (liquid-crystal drive voltage) - Power-saving drive function (standby mode etc.) - Partial liquid crystal drive to display two screens at arbitrary positions - Voltage followers for liquid crystal drive power circuit to fend off the direct current from bleederresistors Step-up circuit generating liquid crystal drive voltage boosted up to 6-time scale 95,040-byte internal RAM Incorporated liquid crystal display driver with 582 source outputs n-raster-row liquid crystal AC drive, enabling polarity inversion by every arbitrary number of rasterrows Internal oscillation, and hardware reset Reversible direction of signals between RAM and source driver Exclusive for Cst structure
*
* *
*
*
*
* * * * * * *
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HD66787
Preliminary
Block Diagram
ENABLE HSYNC PD0 ~ 17 DOTCLK VSYNC Vcc
Index Register (IR)
OSC1 OSC2
18
Control Register (CR) External Display Interfaces VSYNC,HSYNC,DCLK,ENABLE PD17-0
CPG
IM3-1, IM0/ID CS* VLD RS WR*/SCL RD* DB0/SDI, DB1/SDO, ~ DB17 RESET* TEST1 TEST2 TS7-0 SOUT11 SOUT12 SOUT13 SOUT14 SOUT21 SOUT22 SOUT23 SOUT24 VciLVL Vci VciOUT Vci1 VLOUT1 DDVDH VLOUT2 VGH VLOUT3 VGL VLOUT4 VCL
7
16
18
Address Counter (AC) CL1 CL1B FLM SFTCLK DISPTMG M Selector LSEL22 LSEL21 LSEL20 LSEL12 LSEL11 LSEL10
System Interface - 18 bit - 16 bit - 9 bit - 8 bit - Serial Peripheral Interface (SPI) - 3-transmission mode
18
Bit Operation
Timing Generation Circuit
16
18 18
Read Data Latch
18
4 18
Write Data Latch
4
18 4x2
72
Latch Circuit
Level Shift
Graphics RAM (GRAM) 95,040 bytes
Latch Circuit
LCD Drive Circuit
Level Shift
M Alternate Current Circuit
Latch Circuit
S1 ~ S528
Voltage Adjustment Circuit Step-up Circuit 1
Power Supply Circuit
Step-up Circuit 2
Adjustment Circuit
VREG1 Vcom OUT
Grayscale voltage generation Circuit
V0-31
VcomL Vcom VREG1OUT Vc mH
VTEST VGS VMONI V0P,V0N, V31P,V31N
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HD66787
Preliminary
Pin Functions
Signals IM3~1, IM0/ID Number of Pins 4 I/O I Connected to GND or IOVcc Functions Pins to select MPU-interface mode.
IM3 IM2 IM1 IM0/ID MPU-Interface Mode GND GND GND GND GND GND GND GND
IOVcc
DB Pin
GND
IOVcc
Setting disabled Setting disabled 80-system 16-bit interface
_ _ DB17~10, DB8~1 DB17 ~10
GND
GND
GND
IOVcc
IOVcc
80-system 8-bit interface
GND
IOVcc
GND
ID
Serial Peripheral Interface (SPI)
DB1~ 0
GND
IOVcc IOVcc IOVcc
IOVcc
IOVcc
* GND
IOVcc
Setting disabled Setting disabled Setting disabled 80-system 18-bit interface DB17~0
GND GND GND
GND GND
IOVcc
GND
IOVcc
GND
IOVcc
IOVcc
80-system 9-bit interface
DB17~9
IOVcc
IOVcc
*
*
Setting disabled
When Serial Peripheral Interface is selected, IM0 pin is used for the device code ID setting. CS* 1 I MPU Select the HD66787. Low: the HD6678 is selected and accessible High: the HD66787 is not selected and not accessible Must be fixed to the GND level while not used. Indicate whether data is valid or not during RAM write. Low: Valid (Write data to RAM). High: Invalid (Not write data to RAM). RAM address is updated irrespective of VLD. Must be fixed to the GND level while not used. This signal is available when external display interface is used.
CS 0 0 1 VLD 0 1 * RAM Write Valid Invalid Invalid RAM Address Updated Updated Hold
VLD
1
I
MPU
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HD66787
Signals RS Number of Pins 1 I/O I Connected to MPU Functions
Preliminary
Select register. Low: Index/status, High: Control Fix to the "IOVcc" or "GND" level while using SPI. In 80-system bus interface mode, serves as a write strobe signal. Data are written at "Low" level. In Serial Peripheral Interface mode, serves as synchronizing clock signal.
WR*/SCL
1
I
MPU
RD*
1
I
MPU
In 80-system bus interface mode, serves as read-strobe signal. Data are read at the low level of the signal. Fix to the "IOVcc" or "GND" level while using SPI. 18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Unused pins must be fixed to the IOVcc or GND level. Serves as serial data input pin (SDI) in Serial Peripheral Interface mode, where data are input on the rising edge of SCL signal.
DB0/SDI
1
I/O
MPU
DB1/SDO
1
I/O
MPU
18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Unused pins must be fixed to the IOVcc or GND level. Serves as serial data output pin (SDO) in Serial Peripheral Interface mode, where data are output on the falling edge of the SCL signal.
DB2~DB17
16
I/O
MPU
18-bit parallel bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and DB8-DB1 18-bit bus: DB17-DB0 Unused pins must be fixed to the IOVcc or GND level.
ENABLE
1
I
MPU
Indicate whether RAM data are valid or not when RGB interface is used. Low: Selected (access enabled) High: Not selected (access disabled) Must be fixed to the IOVcc or GND level while not used. ENABLE signal invert the polarity according to the setting of EPL resister.
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HD66787
Signals ENABLE Number of Pins 1 I/O I Connected to MPU Functions
EPL ENABLE VLD
Preliminary
RAM Write
RAM Address
0 0 0 1 1 1
0 0 1 0 1 1
0 1 * * 0 1
Valid Invalid Invalid Invalid Valid Invalid
Updated Updated Held Held Updated Updated
VSYNC
1
I
MPU
Frame synchronizing signal. This signal is active low. Must be fixed at the IOVcc level while not used. Line synchronizing signal. This signal is active low. Must be fixed at the IOVcc level while not used. Dot-clock signal This signal is active low The timing of data input is determined at the falling edge of the signal. Must be fixed at the IOVcc level while not used 18-bit bus for RGB data. 6-bit bus: PD17-PD12 16-bit bus: PD17-PD13 and PD11-PD1 18-bit bus: PD17-PD0 Unused pins must be fixed to the IOVcc or GND level.
HSYNC
1
I
MPU
DOTCLK
1
I
MPU
PD0~PD17
18
I
MPU
RESET*
1
I
MPU or reset circuit LCD
Reset pin. Initializes the LSI at the "Low" level. Power-on reset required after turning on the power. Output voltage applied to liquid crystal. The shift direction of segment signals is changeable with SS bit. For example, if SS = 0, RAM address "0000" is output from S1. If SS = 1, it is output from S528. S1, S4, S7, ... display red (R), S2, S5, S8, ... display green (G), and S3, S6, S9, ... display blue (B) (SS = 0).
S1~S528
528
O
LSEL22,21,20 LSEL12,11,10
3 3
I I
GND or IOVcc GND or IOVcc
Output level shift output signals, SOUT24, 23, 22,21. Output level shift output signals, SOUT14, 13, 12,11.
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HD66787
Signals SOUT14,13, 12,11 SOUT24,23, 22,21 Number of Pins 8 I/O O Connected to LCD Functions
Preliminary
Level-shift and then output display clocks. Output pins for SOUT14-11 are arranged on either left or right side of the chip and pins for SOUT24-21 are arranged on the other side of the chip. The kinds of output signals can be selected as shown in the following table with LSEL22-20 and LSEL12-10 bits and output from both or either one side of SOUT14-11 and SOUT 24-21 pins. If signals are output from either one side, halt the operation of unused circuits. When signals are output from SOUT14-11, SOUT 24-21 pins, 6 different kind of 8 level-shift signals are output at maximum. The amplitude of level-shift signal is between VGH and VGL. Pin settings
LSEL 12 LSEL 22 GND GND GND GND IOVcc IOVcc IOVcc IOVcc LSEL 11 LSEL 21 GND GND IOVcc IOVcc GND GND IOVcc IOVcc LSEL 10 LSEL 20 GND IOVcc GND IOVcc GND IOVcc GND IOVcc Halt (VGL)
Level shift signal
SOUT 11 SOUT 21 FLM FLM FLM FLM FLM SOUT 12 SOUT 22 SFTCLK SFTCLK SFTCLK SFTCLK DISPTMG SOUT 13 SOUT 23 CL1 CL1 M M CL1 SOUT 14 SOUT 24 CL1B DISPTMG CL1B DISPTMG CL1B
Setting disabled Setting disabled Halt (VGL) Halt (VGL) Halt (VGL)
Vcom1, Vcom2
2
O
TFT common electrode
Power supply for TFT common electrode. When Vcom AC drive is not selected, output the same level of voltage as VcomL level. When Vcom AC drive is selected, output the voltage with the amplitude between VcomH and VcomL. The AC cycle can be set with M signal. Connect to the TFT common electrode. Reference voltage for VcomH. When adjusting VcomH externally, VcomH internal adjusting circuit must be halted by register setting and place a variable resistor between VREG1OUT and GND to make an adjustment. Otherwise, leave open and adjust VcomH by internal-register setting. High level of Vcom during Vcom AC drive. Connect to a stabilizing capacitor. Vcom voltage when Vcom AC drive is not selected. Low level of Vcom during Vcom AC drive. Voltage can be adjusted with internal registers. Connect to a stabilizing capacitor. When VCOMG bit is set to LOW, a stabilizing capacitor is not necessary because VcomL output is halted. Step-up capacitor connection pins for step-up circuit 1. When the internal step-up circuit is not used, leave open.
VcomR
1
I
Variable resistor or open
VcomH VcomL
1 1
O O
Stabilizing capacitor Stabilizing capacitor or open
C11+, C11-
2
-
Step-up capacitor
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HD66787
Signals C12+, C12C21+, C21C22+, C22OSC1, OSC2 2 I or O Resistor for the oscillator MPU or open Power supply Power supply Number of Pins 6 I/O Connected to Step-up capacitor Functions
Preliminary
Step-up capacitor connection pins for step-up circuit 2. Capacitor connection will be necessary depending on the stepup scale. When the internal step-up circuit is not used, leave open. Connect to an external resistor for R-C oscillation. When supplying clock signals externally, it must be supplied through OSC1 and leave OSC2 open. Frame head pulse with amplitude between GND and Vcc. Use when writing data to RAM in synchronization with FLM. When FLM is not used, leave open. Power supply for analogue circuits. In this case, power supply for the VciOUT amplifier. Connect to an external power supply of 2.5~3.3V. Generates a reference voltage (VciOUT, REGP) in accordance to the ratio set with VC2~0 registers. Connect to the same power supply as the Vci, which has separate wiring from the VciLVL on the FPC.
FLM
1
O
Vci
1
I
VciLVL
1
I
REGP VciOUT
1 1
I/O I
Test pin Stabilizing capacitor, Vci1 VciOUT
Test pin for VREG1OUT. Leave open. Internal reference voltage with amplitude between Vci and GND. Set with VC bit. A reference voltage for the step-up circuit 1. Connect to an external power supply of 2.75V or less when the internal reference voltage is not used.
Vci1
1
I
VLOUT1
1
O
Stabilizing capacitor, DDVDH VLOUT1 Stabilizing capacitor, VGH VLOUT2 Stabilizing capacitor, VGL VLOUT3 Stabilizing capacitor, VCL VLOUT4
Output twice stepped-up Vci1 voltage from the step-up circuit 1. Connect to a stabilizing capacitor. VLOUT1 = 4.0~5.5V Power supply for source driver liquid crystal output portion. A reference voltage for the step-up circuit 2. Output stepped-up DDVDH voltage, which is stepped up to the level Vci1 x 4~6 from the step-up circuit 2. The step-up scale is determined with BT bits. Connect to a stabilizing capacitor. VLOUT2 = max 16.5V Power supply for TFT gate drive. Connect to VLOUT2. Output stepped-up DDVDH voltage, which is stepped up to the level Vci1 x (- 3) ~ (-5) from the step-up circuit 2. The step-up scale is determined with BT bits. Connect to a stabilizing capacitor. VLOUT2 = min -16.5V A power supply for TFT gate drive. Connect to VLOUT3. Output the Vci1 x (-1) voltage from the step-up circuit 2. Connect to a stabilizing capacitor. VLOUT4 = 0 ~ -3.3V Power supply for VcomL drive. Connect to VLOUT4.
DDVDH VLOUT2
1 1
I O
VGH VLOUT3
1 1
I O
VGL VLOUT4
1 1
I O
VCL
1
I
Rev.0.22, May.23.2003, page 12 of 159
HD66787
Signals VREG1OUT Number of Pins 1 I/O I/O Connected to Stabilizing capacitor or power supply Functions
Preliminary
Reference voltage with amplitude between DDVDH and GND, which is generated from the reference voltage internally generated with amplitude between Vci and GND. The scale of output voltage can be set with VRH bits. VREG1OUT becomes (1) a source driver grayscale reference voltage VDH, (2) a VcomH level reference voltage, or (3) a Vcom amplitude reference voltage. Connect to a stabilizing capacitor. VREG1OUT = 3.0 ~ (DDVDH - 0.5)V Power supply for a logic circuit. Vcc = 2.4 ~ 3.3V Power supply for interface pins. IOVcc = 1.8 ~ 3.3V. IOVcc must be turned on with the same voltage as the internal logic voltage Vcc. When it is assembled on COG, connect to Vcc on the FPC to avoid effects from the noise when IOVcc is used. Vcc power supply for RAM. Supply with the same potential as the Vcc. Ground for the logic side. GND = 0V Ground for the analog side. AGND = 0V. When assembled on COG, connect to GND on the FPC to avoid effects from the noise. Ground for internal RAM. RGND = 0V. When assembled on COG, connect to GND on the FPC to avoid effects from the noise. Test pin. Fix it to the GND level. Test pin. Fix it to the GND level. Output from internal positive polarity operational amplifier when the operational amplifier is ON (SAP2-0 = "001", "010", "011", "100", and "101"). Stabilize by connecting to a capacitor. Output from internal negative polarity operational amplifier when the operational amplifier is ON (SAP2-0 = "001", "010", "011", "100", and "101"). Stabilize by connecting to a capacitor. Reference level for grayscale voltage generation circuit. Connect to an external resistor when source driver is used to adjust grayscale levels for each panel. Test pin. Leave open. Test pin. Leave open. Test pin for VcomH. Leave open. Test pin for VcomL. Leave open. Test pin for VcomL. Leave open or connect to a stabilizing capacitor depending on the display quality. Test pin. Leave open. Internal IOVcc level. When neighboring input pins are fixed to the IOVcc side, short-circuit them.
Vcc IOVcc
1 1
-
Power supply Power supply
RVcc GND AGND
1 1 1
-
Power supply Power supply Power supply Power supply GND GND Stabilizing capacitor Stabilizing capacitor GND or external resistor open open open open open open Input pin
RGND
1
-
TEST1 TEST2 V0P, V31P
1 1 2
I I I or O
V0N, V31N
2
I or O
VGS
1
I
VTESTS TS0~TS7 TESTA1 TESTA2 TESTA4 VMONI IOVccDUM1~4
1 8 1 1 1 1 4
I/O O I/O I/O I/O O O
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HD66787
Signals IOGNDDUM1~7 TESTO1~2 DUMMY DUMMYR Number of Pins 7 2 I/O O Connected to Input pin Functions
Preliminary
Internal GND level. When neighboring input pins are fixed to the IOVcc side, short-circuit them. Dummy pads. Leave open. Dummy pad. Leave open. Dummy pad. Leave open.
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HD66787
Preliminary
PAD Arrangement
No.791
VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VLOUT2 VGH VGH VGH VGH VGH VGH VGH VGH DUMMY41 SOUT11 SOUT12 SOUT13 SOUT14
No.769 No.768
1 1
No.1 No.2
DUMMY1 C22+ C22+ C22C22C21+ C21+ C21C21C12+ C12+ C12+ C12+ C12C12C12C12DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 IOGNDDUM1 LSEL12 LSEL11 LSEL10 LSEL20 LSEL21 LSEL22 IM0/ID IM1 IM2 IM3 IOVccDUM1 RESET* DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 IOGNDDUM2 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI IOVccDUM2 RD* WR*/SCL RS CS* VLD IOGNDDUM3 VSYNC HSYNC DOTCLK ENABLE IOVccDUM3 PD17 PD16 PD15 PD14 PD13 PD12 IOGNDDUM4 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FLM IOVcc IOVcc Vcc Vcc Vcc Vcc RVcc RVcc RVcc RVcc RVcc Vci Vci Vci Vci Vci Vci VciLVL RGND RGND RGND RGND RGND RGND AGND AGND AGND AGND AGND GND GND GND GND GND GND TEST1 TEST2 OSC1 OSC2 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TS0 DUMMYR1 DUMMYR2 DUMMYR3 DUMMYR4 DUMMYR5 DUMMYR6 DUMMYR7 DUMMYR8 DUMMYR9 DUMMY11 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 DUMMY18 DUMMY19 DUMMY20 DUMMY21 DUMMY22 DUMMY23 DUMMY24 DUMMY25 DUMMY26 DUMMY27 DUMMY28 DUMMY29 DUMMY30 DUMMY31 DUMMY32 DUMMY33 DUMMY34 DUMMY35 DUMMY36 DUMMY37 DUMMY38 REGP VGS VGS V0P V0N VMONI V31P V31N TESTA4 TESTA1 VcomR VREG1OUT TESTA2 VTESTS VCL VCL VLOUT4 Vci1 Vci1 Vci1 VciOUT VciOUT VciOUT DDVDH DDVDH DDVDH VLOUT1 VLOUT1 C11C11C11C11C11+ C11+ C11+ C11+
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
TESTO2 Vcom1 Vcom1 Vcom1 Vcom1 Vcom1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Min 80um pich 23 pin
1 1 1 1 1 1 1 1 1 1
No.767
No.762
S1 S2 S3 S4 S5
nChip Size : 20.50mmx2.80mm nChip Thickness : 550m (typ.) nPad Coordinate: PAD Center nCoordinate Origin : Chip center nAu bump size : (1) 80m x 80m Corner dummy No.1, No211, No.229, No.768 (2)54mx100m Input : No.2 ~ No.210 , No.230 ~ No.234 , No.763 ~ No.767 (3)100mx54m Input : No.212 ~ No.228 , No.769 ~ No.791 (4)33mx77m Laced LCD output side: No.235 ~ No.762 nAu bump pitch : see PAD coordinate nAu bump height :15m (typ.) nNumbers in the figure indecates numbers of PAD coordinate nAlignment mark (1) Arrangement : 2 places Coordinate(X,Y)= (-9394.4, 1214.7) Coordinate(X,Y)= (9394.4, 1214.7)
100m 50
30
Min 80um pich 209pin
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
100m
Y X
50
30
40
30
(2-a) Coordinate(X,Y) =( -10024.0,1264.6)
50m
30
40
(2-b) Coordinate(X,Y) =( 10024.0,1264.6)
Short-circuit within the chip
20
50m
(3-a)Coordinate (X,Y) = (-10114.6, 1160.7)
5 10 25 25 10 5
10 5
80m
70m
70m 80m
(3-b)Coordinate (X,Y) = (10114.6, 1160.7)
10 25 25 10
10
5 10
25
25
Min 35um pich 538pin
1 1
HD667B87 Laced Output Arrangement Top View
1 1 1 1 1 1 1 1 1 1
S524 S525 S526 S527 S528
25
70m
No.235
1 1 1 1 1 1
Min 80um pich 17 pin
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1
Vcom2 Vcom2 Vcom2 Vcom2 Vcom2
10
25
No.210
DUMMY39
1 1
1 1
TESTO1
No.230
70m
DUMMY40 SOUT21 SOUT22 SOUT23 SOUT24
VcomH VcomH VcomH VcomH VcomH VcomH
VcomL VcomL VcomL VcomL VcomL VcomL
No.211
No.229
No.212
No.228
Rev.0.22, May.23.2003, page 15 of 159
HD66787
Preliminary
PAD Coordinate
pad No pad name X Y pad No pad name X Y pad No pad name X Y pad No pad name X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DUMMY1 C22+ C22+ C22C22C21+ C21+ C21C21C12+ C12+ C12+ C12+ C12C12C12C12DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 IOGNDDUM1 LSEL12 LSEL11 LSEL10 LSEL20 LSEL21 LSEL22 IM0/ID IM1 IM2 IM3 IOVccDUM1 RESET* DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 IOGNDDUM2 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI IOVccDUM2 RD* WR*/SCL RS CS* VLD IOGNDDUM3 VSYNC HSYNC DOTCLK ENABLE IOVccDUM3 PD17 PD16 PD15 PD14 PD13 PD12 IOGNDDUM4 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 FLM IOVcc IOVcc Vcc Vcc Vcc Vcc RVcc RVcc RVcc RVcc
-10114.0 -9885.5 -9805.3 -9725.2 -9645.0 -9564.9 -9484.7 -9404.6 -9324.4 -9186.0 -9105.9 -9025.7 -8945.6 -8807.1 -8727.0 -8646.8 -8566.7 -8433.7 -8353.5 -8273.4 -8193.2 -8113.1 -8032.9 -7952.8 -7872.6 -7792.5 -7618.5 -7501.1 -7421.0 -7340.8 -7260.7 -7180.5 -7100.4 -7020.2 -6940.1 -6859.9 -6779.8 -6635.3 -6512.5 -6372.9 -6292.7 -6212.6 -6132.4 -6052.3 -5972.1 -5892.0 -5811.8 -5731.7 -5587.2 -5469.9 -5389.7 -5309.6 -5229.4 -5149.3 -5069.1 -4989.0 -4908.8 -4828.7 -4684.2 -4566.9 -4486.7 -4406.6 -4326.4 -4246.3 -4101.8 -3984.5 -3904.3 -3824.2 -3744.0 -3599.6 -3482.2 -3402.1 -3321.9 -3241.8 -3161.6 -3081.5 -2937.0 -2819.7 -2739.5 -2659.4 -2579.2 -2499.1 -2418.9 -2338.8 -2258.6 -2178.5 -2098.3 -2018.2 -1938.0 -1857.9 -1702.6 -1622.4 -1478.6 -1398.4 -1307.4 -1227.3 -1083.4 -1003.3 -912.3 -832.1
-1264.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0
101 RVcc -752.0 102 Vci -608.1 103 Vci -528.0 104 Vci -447.8 105 Vci -367.7 106 Vci -287.5 107 Vci -207.4 108 VciLVL -57.7 109 RGND 86.6 110 RGND 166.8 111 RGND 246.9 112 RGND 327.1 113 RGND 407.2 114 RGND 487.4 115 AGND 620.4 116 AGND 700.5 117 AGND 780.7 118 AGND 860.8 119 AGND 941.0 120 GND 1074.0 121 GND 1154.1 122 GND 1287.1 123 GND 1367.3 124 GND 1447.4 125 GND 1527.6 126 TEST1 1679.2 127 TEST2 1759.4 128 OSC1 1899.0 129 OSC2 1979.2 130 TS7 2118.8 131 TS6 2199.0 132 TS5 2279.1 133 TS4 2359.3 134 TS3 2439.4 135 TS2 2519.6 136 TS1 2599.7 137 TS0 2679.9 138 DUMMYR1 2824.3 139 DUMMYR2 2904.5 140 DUMMYR3 2984.6 141 DUMMYR4 3064.8 142 DUMMYR5 3144.9 143 DUMMYR6 3225.1 144 DUMMYR7 3305.2 145 DUMMYR8 3385.4 146 DUMMYR9 3465.5 147 DUMMY11 3598.5 148 DUMMY12 3678.7 149 DUMMY13 3758.8 150 DUMMY14 3839.0 151 DUMMY15 3919.1 152 DUMMY16 3999.3 153 DUMMY17 4079.4 154 DUMMY18 4159.6 155 DUMMY19 4239.7 156 DUMMY20 4319.9 157 DUMMY21 4400.0 158 DUMMY22 4480.2 159 DUMMY23 4560.3 160 DUMMY24 4640.5 161 DUMMY25 4720.6 162 DUMMY26 4800.8 163 DUMMY27 4880.9 164 DUMMY28 4961.1 165 DUMMY29 5041.2 166 DUMMY30 5121.4 167 DUMMY31 5201.5 168 DUMMY32 5281.7 169 DUMMY33 5361.8 170 DUMMY34 5442.0 171 DUMMY35 5522.1 172 DUMMY36 5602.3 173 DUMMY37 5682.4 174 DUMMY38 5762.6 175 REGP 5959.8 176 VGS 6115.4 177 VGS 6241.2 178 V0P 6367.0 179 V0N 6492.9 180 VMONI 6618.7 181 V31P 6744.5 182 V31N 6870.3 183 TESTA4 7020.0 184 TESTA1 7302.8 185 VcomR 7428.6 186 VREG1OUT 7554.4 187 TESTA2 7680.2 188 VTESTS 7806.1 189 VCL 7950.3 190 VCL 8033.1 191 VLOUT4 8113.3 192 Vci1 8251.7 193 Vci1 8331.8 194 Vci1 8412.0 195 VciOUT 8492.1 196 VciOUT 8572.3 197 VciOUT 8652.4 198 DDVDH 8796.3 199 DDVDH 8876.4 200 DDVDH 8956.6
-1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0
201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
VLOUT1 VLOUT1 C11C11C11C11C11+ C11+ C11+ C11+ DUMMY39 VcomL VcomL VcomL VcomL VcomL VcomL VcomH VcomH VcomH VcomH VcomH VcomH DUMMY40 SOUT21 SOUT22 SOUT23 SOUT24 TESTO1 Vcom2 Vcom2 Vcom2 Vcom2 Vcom2 S528 S527 S526 S525 S524 S523 S522 S521 S520 S519 S518 S517 S516 S515 S514 S513 S512 S511 S510 S509 S508 S507 S506 S505 S504 S503 S502 S501 S500 S499 S498 S497 S496 S495 S494 S493 S492 S491 S490 S489 S488 S487 S486 S485 S484 S483 S482 S481 S480 S479 S478 S477 S476 S475 S474 S473 S472 S471 S470 S469 S468 S467 S466 S465 S464 S463
9100.4 9180.6 9324.4 9404.6 9484.7 9564.9 9645.0 9725.2 9805.3 9885.5 10114.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10104.0 10114.0 9892.1 9811.9 9731.8 9651.6 9571.5 9240.0 9205.0 9170.0 9135.0 9100.0 9065.0 9030.0 8995.0 8960.0 8925.0 8890.0 8855.0 8820.0 8785.0 8750.0 8715.0 8680.0 8645.0 8610.0 8575.0 8540.0 8505.0 8470.0 8435.0 8400.0 8365.0 8330.0 8295.0 8260.0 8225.0 8190.0 8155.0 8120.0 8085.0 8050.0 8015.0 7980.0 7945.0 7910.0 7875.0 7840.0 7805.0 7770.0 7735.0 7700.0 7665.0 7630.0 7595.0 7560.0 7525.0 7490.0 7455.0 7420.0 7385.0 7350.0 7315.0 7280.0 7245.0 7210.0 7175.0 7140.0 7105.0 7070.0 7035.0 7000.0 6965.0
-1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1254.0 -1264.0 -1035.5 -897.1 -758.6 -620.2 -481.8 -343.4 -204.9 -66.5 71.9 210.4 348.8 487.2 655.3 788.3 868.4 948.6 1028.7 1264.0 1254.0 1254.0 1254.0 1254.0 1254.0 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5
301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
S462 S461 S460 S459 S458 S457 S456 S455 S454 S453 S452 S451 S450 S449 S448 S447 S446 S445 S444 S443 S442 S441 S440 S439 S438 S437 S436 S435 S434 S433 S432 S431 S430 S429 S428 S427 S426 S425 S424 S423 S422 S421 S420 S419 S418 S417 S416 S415 S414 S413 S412 S411 S410 S409 S408 S407 S406 S405 S404 S403 S402 S401 S400 S399 S398 S397 S396 S395 S394 S393 S392 S391 S390 S389 S388 S387 S386 S385 S384 S383 S382 S381 S380 S379 S378 S377 S376 S375 S374 S373 S372 S371 S370 S369 S368 S367 S366 S365 S364 S363
6930.0 6895.0 6860.0 6825.0 6790.0 6755.0 6720.0 6685.0 6650.0 6615.0 6580.0 6545.0 6510.0 6475.0 6440.0 6405.0 6370.0 6335.0 6300.0 6265.0 6230.0 6195.0 6160.0 6125.0 6090.0 6055.0 6020.0 5985.0 5950.0 5915.0 5880.0 5845.0 5810.0 5775.0 5740.0 5705.0 5670.0 5635.0 5600.0 5565.0 5530.0 5495.0 5460.0 5425.0 5390.0 5355.0 5320.0 5285.0 5250.0 5215.0 5180.0 5145.0 5110.0 5075.0 5040.0 5005.0 4970.0 4935.0 4900.0 4865.0 4830.0 4795.0 4760.0 4725.0 4690.0 4655.0 4620.0 4585.0 4550.0 4515.0 4480.0 4445.0 4410.0 4375.0 4340.0 4305.0 4270.0 4235.0 4200.0 4165.0 4130.0 4095.0 4060.0 4025.0 3990.0 3955.0 3920.0 3885.0 3850.0 3815.0 3780.0 3745.0 3710.0 3675.0 3640.0 3605.0 3570.0 3535.0 3500.0 3465.0
1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5
Rev.0.22, May.23.2003, page 16 of 159
HD66787
pad No pad name X Y pad No pad name X Y pad No pad name X Y pad No pad name
Preliminary
X Y
401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
S362 S361 S360 S359 S358 S357 S356 S355 S354 S353 S352 S351 S350 S349 S348 S347 S346 S345 S344 S343 S342 S341 S340 S339 S338 S337 S336 S335 S334 S333 S332 S331 S330 S329 S328 S327 S326 S325 S324 S323 S322 S321 S320 S319 S318 S317 S316 S315 S314 S313 S312 S311 S310 S309 S308 S307 S306 S305 S304 S303 S302 S301 S300 S299 S298 S297 S296 S295 S294 S293 S292 S291 S290 S289 S288 S287 S286 S285 S284 S283 S282 S281 S280 S279 S278 S277 S276 S275 S274 S273 S272 S271 S270 S269 S268 S267 S266 S265 S264 S263
3430.0 3395.0 3360.0 3325.0 3290.0 3255.0 3220.0 3185.0 3150.0 3115.0 3080.0 3045.0 3010.0 2975.0 2940.0 2905.0 2870.0 2835.0 2800.0 2765.0 2730.0 2695.0 2660.0 2625.0 2590.0 2555.0 2520.0 2485.0 2450.0 2415.0 2380.0 2345.0 2310.0 2275.0 2240.0 2205.0 2170.0 2135.0 2100.0 2065.0 2030.0 1995.0 1960.0 1925.0 1890.0 1855.0 1820.0 1785.0 1750.0 1715.0 1680.0 1645.0 1610.0 1575.0 1540.0 1505.0 1470.0 1435.0 1400.0 1365.0 1330.0 1295.0 1260.0 1225.0 1190.0 1155.0 1120.0 1085.0 1050.0 1015.0 980.0 945.0 910.0 875.0 840.0 805.0 770.0 735.0 700.0 665.0 630.0 595.0 560.0 525.0 490.0 455.0 420.0 385.0 350.0 315.0 280.0 245.0 210.0 175.0 140.0 105.0 70.0 35.0 -35.0 -70.0
1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5
501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
S262 S261 S260 S259 S258 S257 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163
-105.0 -140.0 -175.0 -210.0 -245.0 -280.0 -315.0 -350.0 -385.0 -420.0 -455.0 -490.0 -525.0 -560.0 -595.0 -630.0 -665.0 -700.0 -735.0 -770.0 -805.0 -840.0 -875.0 -910.0 -945.0 -980.0 -1015.0 -1050.0 -1085.0 -1120.0 -1155.0 -1190.0 -1225.0 -1260.0 -1295.0 -1330.0 -1365.0 -1400.0 -1435.0 -1470.0 -1505.0 -1540.0 -1575.0 -1610.0 -1645.0 -1680.0 -1715.0 -1750.0 -1785.0 -1820.0 -1855.0 -1890.0 -1925.0 -1960.0 -1995.0 -2030.0 -2065.0 -2100.0 -2135.0 -2170.0 -2205.0 -2240.0 -2275.0 -2310.0 -2345.0 -2380.0 -2415.0 -2450.0 -2485.0 -2520.0 -2555.0 -2590.0 -2625.0 -2660.0 -2695.0 -2730.0 -2765.0 -2800.0 -2835.0 -2870.0 -2905.0 -2940.0 -2975.0 -3010.0 -3045.0 -3080.0 -3115.0 -3150.0 -3185.0 -3220.0 -3255.0 -3290.0 -3325.0 -3360.0 -3395.0 -3430.0 -3465.0 -3500.0 -3535.0 -3570.0
1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5
601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700
S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63
-3605.0 -3640.0 -3675.0 -3710.0 -3745.0 -3780.0 -3815.0 -3850.0 -3885.0 -3920.0 -3955.0 -3990.0 -4025.0 -4060.0 -4095.0 -4130.0 -4165.0 -4200.0 -4235.0 -4270.0 -4305.0 -4340.0 -4375.0 -4410.0 -4445.0 -4480.0 -4515.0 -4550.0 -4585.0 -4620.0 -4655.0 -4690.0 -4725.0 -4760.0 -4795.0 -4830.0 -4865.0 -4900.0 -4935.0 -4970.0 -5005.0 -5040.0 -5075.0 -5110.0 -5145.0 -5180.0 -5215.0 -5250.0 -5285.0 -5320.0 -5355.0 -5390.0 -5425.0 -5460.0 -5495.0 -5530.0 -5565.0 -5600.0 -5635.0 -5670.0 -5705.0 -5740.0 -5775.0 -5810.0 -5845.0 -5880.0 -5915.0 -5950.0 -5985.0 -6020.0 -6055.0 -6090.0 -6125.0 -6160.0 -6195.0 -6230.0 -6265.0 -6300.0 -6335.0 -6370.0 -6405.0 -6440.0 -6475.0 -6510.0 -6545.0 -6580.0 -6615.0 -6650.0 -6685.0 -6720.0 -6755.0 -6790.0 -6825.0 -6860.0 -6895.0 -6930.0 -6965.0 -7000.0 -7035.0 -7070.0
1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5
701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791
S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 Vcom1 Vcom1 Vcom1 Vcom1 Vcom1 TESTO2 SOUT14 SOUT13 SOUT12 SOUT11 DUMMY41 VGH VGH VGH VGH VGH VGH VGH VGH VLOUT2 VGL VGL VGL VGL VGL VGL VGL VGL VLOUT3
-7105.0 -7140.0 -7175.0 -7210.0 -7245.0 -7280.0 -7315.0 -7350.0 -7385.0 -7420.0 -7455.0 -7490.0 -7525.0 -7560.0 -7595.0 -7630.0 -7665.0 -7700.0 -7735.0 -7770.0 -7805.0 -7840.0 -7875.0 -7910.0 -7945.0 -7980.0 -8015.0 -8050.0 -8085.0 -8120.0 -8155.0 -8190.0 -8225.0 -8260.0 -8295.0 -8330.0 -8365.0 -8400.0 -8435.0 -8470.0 -8505.0 -8540.0 -8575.0 -8610.0 -8645.0 -8680.0 -8715.0 -8750.0 -8785.0 -8820.0 -8855.0 -8890.0 -8925.0 -8960.0 -8995.0 -9030.0 -9065.0 -9100.0 -9135.0 -9170.0 -9205.0 -9240.0 -9571.5 -9651.6 -9731.8 -9811.9 -9892.1 -10114.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0 -10104.0
1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1148.5 1265.5 1254.0 1254.0 1254.0 1254.0 1254.0 1264.0 1028.7 948.6 868.4 788.3 655.3 512.8 432.6 352.5 272.3 192.2 112.0 31.9 -48.3 -181.3 -341.4 -421.6 -501.7 -581.9 -662.0 -742.2 -822.3 -902.5 -1035.5
Alignment Mark
L-type (Positive) L-type (Negative) Circle (Positive) Circle (Negative) Cross
X
Y
-10114.6 10114.6 -10024.0 10024.0 -9394.4 9394.4
1160.7 1160.7 1264.6 1264.6 1214.7 1214.7
Rev.0.22, May.23.2003, page 17 of 159
HD66787
Preliminary
BUMP Arrangements (T.B.D.)
Rev.0.22, May.23.2003, page 18 of 159
HD66787
Preliminary
Block Function
1. System Interface
The HD66787 has five high-speed system interfaces: 80-system 18-/16-/9-/8-bit bus and Serial Peripheral Interface (SPI) port. The interface mode is selected with IM3-0 pins. The HD66787 has three registers: 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit read-data register (RDR). The IR stores index information from control registers and GRAM. The WDR temporarily stores data to write into the control registers and GRAM, and the RDR temporarily stores data read from GRAM. Data written into GRAM from the MPU is first written into the WDR and then automatically written into GRAM by internal operation. Since data are read through the RDR from GRAM, the data read out first are invalid data and the ensuing data are read out normally. The execution time for instructions other than oscillation start is 0-clock cycle, which enables writing instructions consecutively. Register Selection (8/9/16/18 Parallel Interfaces)
80-system Bus WR* 0 1 0 1 RD* 1 0 1 0 RS 0 0 1 1 Operation Write index to IR Read internal status Write to the control registers or GRAM through WDR Read from GRAM through RDR
Values of CS and VLD during RAM Write
CS* 0 1 0 1 VLD 0 0 1 1 Operations Write data to GRAM. RAM address is updated. Not write data to GRAM. RAM address is not updated. Not write data to GRAM. RAM address is updated. Not write data to GRAM. RAM address is not updated.
Note 1) The VLD setting is only effective with RAM write instructions.
Register Selection (Serial Peripheral Interface)
Start bytes R/W 0 1 0 1 RS 0 0 1 1 Operations Write index to IR Read internal status Write into the control register and GRAM through WDR Read from GRAM through RDR
Rev.0.22, May.23.2003, page 19 of 159
HD66787 2. External Display Interface
Preliminary
The HD66787 incorporates RGB and VSYNC interfaces as an external interface for displaying moving pictures. When RGB-I/F is selected, the display operation is executed in synchronization with the externally supplied signals, VSYNC, HSYNC, and DOTCLK. The display data (PD17-0) are written according to the values of data enable signal (ENABLE) and data valid signal (VLD) in synchronization with VSYNC, HSYNC, and DOTCLK signals. This data write method allows flicker-free screen update. When VSYNC-I/F is selected, operations other than the frame synchronization by VSYNC signal are synchronized with internal clocks. The display data are written to GRAM through a system interface. In this case, there are constraints on the timing and methods of RAM update. See the "External Display Interface" section for more details. Switching between conventional system interfaces and external display interfaces is made through instructions. An optimum interface is selected whether the screen is displaying moving or still pictures. All data written through RGB-I/F are written to GRAM. Therefore, data is transmitted only when the screen is being updated, which reduces the amount of data transmission, thereby saving power when moving pictures are being displayed. 3. Bit Operations
The HD66787 supports a write data mask function that selects and writes data into GRAM by bit, and performs logical operation or conditional rewrite on the contents of compare registers and the data to write to GRAM. For details, see the "Graphics Operation Functions" section. 4. Address Counter (AC)
Address counter (AC) assigns address to GRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing data to GRAM, the AC is automatically updated plus or minus 1. The AC is not updated when the data are read from GRAM. Window address function enables data write only in the rectangular area of GRAM specified by the window address. 5. Graphics RAM (GRAM)
GRAM is a graphics RAM that stores bit-pattern data of 176 x 240 bytes with 18 bits per pixel. 6. Grayscale Power Supply Voltage Generating Circuit
Grayscale voltage generation circuit generates liquid crystal drive voltage according to the grayscale data set in the -correction register, enabling 262,144-color display. For details, see the "-Correction Register" section. 7. Timing Generator
Timing generator generates timing signals for the operation of internal circuits such as GRAM. The timing for display operation such as RAM read and the internal operation timing such as access from MPU are generated in a way to avoid mutual interfere. The interface signals (M, FLM, CL1, EQ, DCCLK,
Rev.0.22, May.23.2003, page 20 of 159
HD66787
Preliminary
DISPTMG, and SFTCLK) are generated internally, and a part of the signals is output through a level transforming circuit. 8. Oscillation Circuit (OSC)
The HD66787 can provide R-C oscillation simply by placing an external oscillation-resistor between OSC1 and OSC2 pins. An appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can be supplied externally. Since R-C oscillation is halted during the standby mode, current consumption will be reduced. For details, see the "Oscillation Circuit" section. 9. LCD Driver Circuit
The LCD driver circuit of HD66787 consists of a 528-output source driver (S1 ~ S528). Display pattern data are latched when 528-bit data arrive. The latched data controls the source driver and generates drive waveforms. The shift direction of outputting 528 bits from source driver is changeable with the SS bit. Select an appropriate shift direction for an assembly. 10. LCD Drive Power Supply Circuit The LCD drive power supply circuit of HD66787 generates voltages V0, V31P, V31N, VGH, and Vcom required for driving LCD. 11. LTPS Panel Interface Circuit LTPS Panel Interface Circuit level-shifts and outputs display clock signal to control LTPS (gate-less) panel. Output pins arranged on both sides of the LSI allow flexible panel design. The LSEL22-20 pins allows a combination of display clocks from SOUT24-21 and the LSEL12-10 pins allows a combination of display clocks from SOUT14-11.
Rev.0.22, May.23.2003, page 21 of 159
HD66787
Preliminary
GRAM Address MAP
S517
S518
S519
S520
S521
S522
S523
S524
S525
S526
S527 ......
SG pin
............
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20
......
PD PD PD PD PD PD PD PD 17 ... 0 17 ... 0 17 ... 0 17 ... 0 "0000"H "0001"H "0002"H "0003"H "0100"H "0101"H "0102"H "0103"H "0200"H "0201"H "0202"H "0203"H "0300"H "0301"H "0302"H "0303"H "0400"H "0401"H "0402"H "0403"H "0500"H "0501"H "0502"H "0503"H "0600"H "0601"H "0602"H "0603"H "0700"H "0701"H "0702"H "0703"H "0800"H "0801"H "0802"H "0803"H "0900"H "0901"H "0902"H "0903"H "0A00"H "0A01"H "0A02"H "0A03"H "0B00"H "0B01"H "0B02"H "0B03"H "0C00"H "0C01"H "0C02"H "0C03"H "0D00"H "0D01"H "0D02"H "0D03"H "0E01"H "0E02"H "0E03"H "0E00"H "0F00"H "0F01"H "0F02"H "0F03"H "1000"H "1001"H "1002"H "1003"H "1100"H "1101"H "1102"H "1103"H "1200"H "1201"H "1202"H "1203"H "1300"H "1301"H "1302"H "1303"H
...... ...... ...... ......
............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............
PD PD 17 ... 0 "00AC"H "01AC"H "02AC"H "03AC"H "04AC"H "05AC"H "06AC"H "07AC"H "08AC"H "09AC"H "0AAC"H "0BAC"H "0CAC"H "0DAC"H "0EAC"H "0FAC"H "10AC"H "11AC"H "12AC"H "13AC"H
......
PD PD 17 ... 0 "00AD"H "01AD"H "02AD"H "03AD"H "04AD"H "05AD"H "06AD"H "07AD"H "08AD"H "09AD"H "0AAD"H "0BAD"H "0CAD"H "0DAD"H "0EAD"H "0FAD"H "10AD"H "11AD"H "12AD"H "13AD"H
......
PD PD 17 ... 0 "00AE"H "01AE"H "02AE"H "03AE"H "04AE"H "05AE"H "06AE"H "07AE"H "08AE"H "09AE"H "0AAE"H "0BAE"H "0CAE"H "0DAE"H "0EAE"H "0FAE"H "10AE"H "11AE"H "12AE"H "13AE"H "E8AE"H "E9AE"H "EAAE"H "EBAE"H "ECAE"H "EDAE"H "EEAE"H "EFAE"H
......
PD PD 17 ... 0 "00AF"H "01AF"H "02AF"H "03AF"H "04AF"H "05AF"H "06AF"H "07AF"H "08AF"H "09AF"H "0AAF"H "0BAF"H "0CAF"H "0DAF"H "0EAF"H "0FAF"H "10AF"H "11AF"H "12AF"H "13AF"H "E8AF"H "E9AF"H "EAAF"H "EBAF"H "ECAF"H "EDAF"H "EEAF"H "EFAF"H
G233 G234 G235 G236 G237 G238 G239 G240
"0800"H "0900"H "EA00"H "EB00"H "EC00"H "ED00"H "EE00"H "EF00"H
"0801"H "0901"H "EA01"H "EB01"H "EC01"H "ED01"H "EE01"H "EF01"H
"0802"H "0902"H "EA02"H "EB02"H "EC02"H "ED02"H "EE02"H "EF02"H
"0803"H "0903"H "EA03"H "EB03"H "EC03"H "ED03"H "EE03"H "EF03"H
"E8AC"H "E9AC"H "EAAC"H "EBAC"H "ECAC"H "EDAC"H "EEAC"H "EFAC"H
"E8AD"H "E9AD"H "EAAD"H "EBAD"H "ECAD"H "EDAD"H "EEAD"H "EFAD"H
GRAM address and display panel position (SS ="0")
Rev.0.22, May.23.2003, page 22 of 159
S528
S10
S11
S12
S1
S2
S3
S4
S5
S6
S7
S8
S9
HD66787
80-System 18-Bit Interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1 DB 0
Preliminary
RGB Arrangement Output pin
R5
R4
R3 R2 S (3n + 1)
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 2)
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
80-System 16-Bit Interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1
RGB Arrangement Output pin
R5
R4
R3 R2 S (3n + 1)
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 2)
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
80-System 9-Bit Interface 1st Transmission
GRAM Data DB 17 DB 16 DB 15 DB DB 14 13 DB 12 DB 11 DB 10 DB DB 9 17
2nd Transmission
DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB DB 10 9
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 1)
S (3n + 2)
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
80-System 8-Bit Interface/SPI (2 transmissions/pixel) 1st Transmission
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 17
2nd Transmission
DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10
RGB Arrangement Output pin
R5
R4
R3 R2 S (3n + 1)
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 2)
S (3n + 3)
Note: n = lower eight bits of address (0 to 175)
GRAM data and RGB assignment (SS = "0", BGR = "0")
Rev.0.22, May.23.2003, page 23 of 159
HD66787
18-bit RGB interface
GRAM Data PD PD PD PD PD PD 17 16 15 14 13 12 PD PD PD PD PD PD PD PD PD PD 11 10 9 8 7 6 5 4 3 2 PD PD 1 0
Preliminary
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 1)
S (3n + 2)
S (3n + 3)
16-bit RGB interface
GRAM Data PD PD PD PD PD 17 16 15 14 13 PD PD PD PD PD PD PD PD PD PD 11 10 9 8 7 6 5 4 3 2 PD 1
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 1)
S (3n + 2)
S (3n + 3)
6-bit RGB interface
1st Transmission 2nd Transmission 3rd Transmission
GRAM Data
PD 17
PD PD PD 16 15 14
PD PD 13 12
PD PD PD PD PD 17 16 15 14 13
PD PD 12 17
PD PD PD 16 15 14
PD PD 13 12
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (3n + 1)
S (3n + 2)
S (3n + 3)
GRAM data and RGB assignment (SS = "0", BGR = "0")
Rev.0.22, May.23.2003, page 24 of 159
HD66787
Preliminary
S517
S518
S519
S520
S521
S523
S524
S525
S526
S527 ......
SG pin
............
......
......
......
......
......
......
......
G233 G234 G235 G236 G237 G238 G239 G240
"E8AF"H "E9AF"H "EAAF"H "EBAF"H "ECAF"H "EDAF"H "EEAF"H "EFAF"H
"E8AE"H "E9AE"H "EAAE"H "EBAE"H "ECAE"H "EDAE"H "EEAE"H "EFAE"H
"E8AD"H "E9AD"H "EAAD"H "EBAD"H "ECAD"H "EDAD"H "EEAD"H "EFAD"H
"E8AC"H "E9AC"H "EAAC"H "EBAC"H "ECAC"H "EDAC"H "EEAC"H "EFAC"H
............ "0803"H ............ "0903"H ............ "EA03"H ............ "EB03"H ............ "EC03"H ............ "ED03"H ............ "EE03"H ............ "EF03"H
"0802"H "0902"H "EA02"H "EB02"H "EC02"H "ED02"H "EE02"H "EF02"H
"0801"H "0901"H "EA01"H "EB01"H "EC01"H "ED01"H "EE01"H "EF01"H
......
G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20
PD PD 17 ... 0 "00AF"H "01AF"H "02AF"H "03AF"H "04AF"H "05AF"H "06AF"H "07AF"H "08AF"H "09AF"H "0AAF"H "0BAF"H "0CAF"H "0DAF"H "0EAF"H "0FAF"H "10AF"H "11AF"H "12AF"H "13AF"H
PD PD 17 ... 0 "00AE"H "01AE"H "02AE"H "03AE"H "04AE"H "05AE"H "06AE"H "07AE"H "08AE"H "09AE"H "0AAE"H "0BAE"H "0CAE"H "0DAE"H "0EAE"H "0FAE"H "10AE"H "11AE"H "12AE"H "13AE"H
PD PD 17 ... 0 "00AD"H "01AD"H "02AD"H "03AD"H "04AD"H "05AD"H "06AD"H "07AD"H "08AD"H "09AD"H "0AAD"H "0BAD"H "0CAD"H "0DAD"H "0EAD"H "0FAD"H "10AD"H "11AD"H "12AD"H "13AD"H
PD PD 17 ... 0 "00AC"H "01AC"H "02AC"H "03AC"H "04AC"H "05AC"H "06AC"H "07AC"H "08AC"H "09AC"H "0AAC"H "0BAC"H "0CAC"H "0DAC"H "0EAC"H "0FAC"H "10AC"H "11AC"H "12AC"H "13AC"H
............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............
PD PD PD PD PD PD PD PD 17 ... 0 17 ... 0 17 ... 0 17 ... 0 "0003"H "0002"H "0001"H "0000"H "0103"H "0102"H "0101"H "0100"H "0203"H "0202"H "0201"H "0200"H "0303"H "0302"H "0301"H "0300"H "0403"H "0402"H "0401"H "0400"H "0503"H "0502"H "0501"H "0500"H "0603"H "0602"H "0601"H "0600"H "0703"H "0702"H "0701"H "0700"H "0803"H "0802"H "0801"H "0800"H "0903"H "0902"H "0901"H "0900"H "0A03"H "0A02"H "0A01"H "0A00"H "0B03"H "0B02"H "0B01"H "0B00"H "0C03"H "0C02"H "0C01"H "0C00"H "0D03"H "0D02"H "0D01"H "0D00"H "0E03"H "0E02"H "0E01"H "0E00"H "0F03"H "0F02"H "0F01"H "0F00"H "1003"H "1002"H "1001"H "1000"H "1103"H "1102"H "1101"H "1100"H "1203"H "1202"H "1201"H "1200"H "1303"H "1302"H "1301"H "1300"H "0800"H "0900"H "EA00"H "EB00"H "EC00"H "ED00"H "EE00"H "EF00"H
GRAM address and display panel position (SS ="1", BGR "1")
Rev.0.22, May.23.2003, page 25 of 159
S528
S522
S10
S11
S12
S1
S2
S3
S4
S5
S6
S7
S8
S9
HD66787
80-system 18-bit interface
GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0
Preliminary
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
80-system 16-bit interface
GRAM Data DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
80-system 9-bit interface
1st Transmission 2nd Transmission
GRAM Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB DB 9 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
80-system 8-bit interface/SPI (2 transmissions/pixel)
1st Transmission 2nd Transmission
GRAM Data
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
RGB Arrangement Output pin
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note: n = lower eight bits of address (0 to 175)
GRAM data and RGB assignment (SS = "1", BGR = "1")
Rev.0.22, May.23.2003, page 26 of 159
HD66787
80-system 8 -bit interface (3 transmissions / pixel, 262k color mode : TRI = 1, DFM1 - 0 =10)
1st Transmission 2nd Transmission 3rd Transmission
Preliminary
GRAM Data PD PD PD PD 17 16 15 14
PD PD 13 12
PD PD 17 16
PD PD 15 14
PD PD PD PD PD PD 13 12 17 16 15 14
PD PD 13 12
RGB Arrangement Output pin
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~175)
80-system 8-bit interface (3 transmissions/pixel, 65k color mode : TRI = 1, DFM1 - 0 = 11)
1st Transmission 2nd Transmission 3rd Transmission
GRAM Data PD PD 17 16
PD PD 15 14
PD PD 13 12
PD PD 17 16
PD PD PD PD PD PD 15 14 13 12 17 16
PD PD 15 14
PD PD 13 12
RGB Arrangement Output pin
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~175)
GRAM data and RGB assignment (SS = "1", BGR = "1")
Rev.0.22, May.23.2003, page 27 of 159
HD66787
18- bit RGB interface
Preliminary
GRAM Data PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB R5 Arrangement Output pin
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~ 175)
16- bit RGB interface
GRAM Data PD PD PD PD PD 17 16 15 14 13 PD PD PD PD PD PD PD PD PD PD 11 10 9 8 7 6 5 4 3 2 PD 1
RGB Arrangement Output pin
R5
R4
R3 R2 S (528 - 3n)
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (527 - 3n)
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~ 175)
6- bit RGB interface
1st Transmission 2nd Transmission 3rd Transmission
GRAM Data PD PD PD PD PD PD 17 16 15 14 13 12
PD PD PD PD 17 16 15 14
PD PD PD PD PD PD PD PD 13 12 17 16 15 14 13 12
RGB Arrangement Output pin
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
S (528 - 3n)
S (527 - 3n)
S (526 - 3n)
Note : n = Lower 8 bits of address (0 ~ 175)
GRAM data and RGB assignment (SS = "1", BGR = "1")
Rev.0.22, May.23.2003, page 28 of 159
HD66787
Preliminary
Instructions
Outline The HD66787 adapts 18-bit bus architecture that enables high-speed interfacing with a high-performance microcomputer. Data sent from external (18/16/9/8 bits) are stored temporarily in the instruction register (IR) and the data register (DR) to store control information before internal operation starts. Since internal operation is decided according to the signal sent from the microcomputer, register selection signal (RS), read/write signal (R/W), and internal 16-bit data bus signal (DB15 to DB0) are called instruction. GRAM is accessed through internal 18-bit data bus. There are eight categories of instructions: 1. 2. 3. 4. 5. 6. 7. 8. Specify index Read status Control display Control power management Process graphics data Set internal GRAM address Transfer data to and from internal GRAM Set grayscale level for internal grayscale -adjustment
Normally, the 7th instruction to write display data is executed the most frequently. The address of internal GRAM is updated automatically after data are written to the internal GRAM. With the window address function, this reduces the amount of data transmission to minimum and thereby lightens the load on the program in the microcomputer. Since instructions are executed in 0 cycle, it is possible to write instructions consecutively. As the following figure shows, the assignment to the 16 instruction bits (IB15-0) varies according to the interface in use. An instruction must adopt the data format for each interface. .
Rev.0.22, May.23.2003, page 29 of 159
HD66787
80-system 18-bit interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1
Preliminary
DB 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB IB 54
IB 3
IB 2
IB 1
IB 0
80-system 16-bit interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
80-system 9-bit interface
1st Transmission 2nd Transmission
GRAM Data DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB DB 9 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 9
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
80-system 8-bit interface / SPI(2/3 transmissions)
1st Transmission 2nd Transmission
GRAM Data DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction bits Instruction Descriptions The following are detail explanations of instructions with illustrations of instruction bits (IB15-0) assigned to each interface. Index The index instruction specifies the index (R00h to R4Fh) of control register and RAM control. It sets the register number from 0000000 to 1111111 in binary form. Do not try to access to the register to which the index is not assigned.
R/W W RS 0 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 ID6 IB5 ID5 IB4 ID4 IB3 ID3 IB2 ID2 IB1 ID1 IB0 ID0
Rev.0.22, May.23.2003, page 30 of 159
HD66787 Status Read The status read instruction reads the internal status of the HD66787. L7-0: Indicate the position of raster-row driving liquid crystal.
R/W R RS 0 IB15 IB14 IB13 IB12 IB11 IB10 IB9 L7 L6 L5 L4 L3 L2 L1 IB8 L0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 0
Preliminary
IB2 0
IB1 0
IB0 0
Start Oscillation (R00h) The start oscillation instruction restarts the oscillator in a halt state during the standby mode. After executing this instruction, wait at least 10 ms for stabilizing oscillation before issuing a next instruction. For details, see the "Standby Mode" section. "0787"H is read out, if this register is forced to read out.
R/W W
RS 1 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0 1 1
0 0 0 0 0 1 1 1 1 0 0 0 0 1 1
R
Driver Output Control (R01h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 0
VSPL HSPL DPL EPL
IB8 SS
IB7 0
IB6 0
IB5 0
IB4
IB3
IB2
IB1
IB0
0
0
NL4 NL3 NL2 NL1 NL0
SS: Select the shift direction of outputs from the source driver. When SS = 0, the shift direction of outputs is from S1 to S528. When SS = 1, the shift direction of output is from S528 to S1. In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins. To assign R, G, B dots to the source driver pins interchangeably from S1, set SS = 0, BGR = 0. To assign R, G, B dots to the source driver pins interchangeably from S528, set SS = 1, BGR = 1. EPL: Set the polarity of ENABLE pin while using RGB interface. EPL = "0" EPL ="1" : ENABLE = "Low" / Write data to PD17-0. : ENABLE = "High" / Data write invalid. : ENABLE = "High" / Write data to PD17-0. : ENABLE = "Low" / Data write invalid.
Rev.0.22, May.23.2003, page 31 of 159
HD66787
Preliminary
The following table shows the relationship between EPL, ENABLE, VLD and RAM access.
EPL 0 0 0 1 1 1 ENABLE 0 0 1 0 1 1 VLD 0 1 * * 0 1 RAM write Valid Invalid Invalid Invalid Valid Invalid RAM address Updated Updated Hold Hold Updated Updated
VSPL: Invert the polarity of signal for VSYNC pin. VSPL = "0" VSPL = "1" : Low active. : High active.
HSPL: Invert the polarity of signal for HSYNC pin. HSPL = "0" HSPL = "1" : Low active. : High active.
DPL: Invert the polarity of signal for DOTCLK pin. DPL = "0" DPL = "1" : Data are read in synchronization with the rising edge of the DOTCLK. : Data are read in synchronization with the falling edge of the DOTCLK.
NL4-0: Specify the number of LCD drive raster-rows. The number of drive raster-rows is changeable by 8 multiples. The GRAM address mapping is independent of this setting. Select a number of raster-rows that the display size covers the size of a panel.
Rev.0.22, May.23.2003, page 32 of 159
HD66787 NL bits
NL4 0 0 0 0 0 0 0 0 0 NL3 0 0 0 0 0 0 0 0 1 NL2 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 NL1 0 0 1 1 0 0 1 1 0 NL0 0 1 0 1 0 1 0 1 0 Display Size Setting disabled 528 x 16 dots 528 x 24 dots 528 x 32 dots 528 x 40 dots 528 x 48 dots 528 x 56 dots 528 x 64 dots 528 x 72 dots 528 x 200 dots 528 x 208 dots 528 x 216 dots 528 x 224 dots 528 x 232 dots 528 x 240 dots Liquid crystal drive raster-rows Setting disabled 16 24 32 40 48 56 64 72 200 208 216 224 232 240
Preliminary
Gate Driver Lines Used Setting disabled G1-G16 G1-G24 G1-G32 G1-G40 G1-G48 G1-G56 G1-G64 G1-G72 G1-G200 G1-G208 G1-G216 G1-G224 G1-G232 G1-G240
Note 1) A front porch period (set in the FP register) and a back porch period (set in the BP register) will be inserted as a blank period before and after driving all gate lines.
LCD Driving Waveform Control (R02h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 1 B/C
IB8 EOR
IB7 0
IB6 0
IB5
IB4
IB3
IB2
IB1
IB0
NW5 NW4 NW3 NW2 NW1 NW0
NW5-0: Specify n, the number of raster-rows from 1 to 64 to alternate every n+1 raster-rows when Cpattern waveform is generated (B/C = 1). EOR: When EOR = 1 and a C-pattern waveform is generated (B/C =1), an odd/even frame select signal and an n-raster-row inversion signal are AC-driven. This instruction is available when liquid crystal AC drive is not made depending on the combination of numbers of LCD drive raster-rows and the value of "n" of n-raster-row inversion AC drive. For details, see "n-raster-row inversion AC drive".
Rev.0.22, May.23.2003, page 33 of 159
HD66787
Preliminary
B/C: When B/C =0, a field AC waveform is generated. Alternation occurs every frame when driving liquid crystal. When B/C=1, alternation occurs every n raster-row. For details, see the "n-raster-row Inversion AC Drive" section. Entry Mode (R03h) Compare Register 1 (R04h) Compare Register 2 (R05h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 TRI DFM1 DFM0 BGR 0 0 HWM IB8 0 IB7 0 IB6 0 IB5 IB4 IB3 AM IB2 IB1 IB0
I/D1 I/D0
LG2 LG1 LG0
W W
1 1
0 0
0 0
CP11 CP10 CP9 0 0 0
CP8 0
CP7 0
CP6 0
0 0
0 0
CP5
CP4
CP3
CP2
CP1
CP0
CP17 CP16 CP15 CP14 CP13 CP12
The HD66787 modifies write data sent from the microcomputer before writing to GRAM. This enables high-speed GRAM data update, and reduces the load on the microcomputer software. For details, see the "Graphics Operation Function" section. TRI: RAM write data are transmitted in 3 times through 8-bit interface when TRI = 1. When 8-bit interface mode is not selected, set TRI to 0. DFM1-0: Specify the data format for RAM write data transmission when TRI = 1 (8-bit interface mode only). DFM1-0 = "10" : 262k mode (6bit x 3 transmissions) DFM1-0 = "11" : 65k mode (5,6,5 bits transmissions) HWM: When HWM=1, data are written to GRAM in high speed. In high-speed write mode, 4 words are written to GRAM in a single operation after executing 4 RAM write operations. If RAM write is terminated before it is executed 4 times, the last data will not be written. Make sure that RAM write is executed 4 times. For this reason, the lower 2 bits must be set to "0" when setting the RAM address. For details, see "High-Speed RAM Write Mode" section. I/D1-0: The address counter is automatically incremented by 1, after data are written to GRAM when I/D10 = "1". The address counter is automatically decremented by 1, after data are written to GRAM when I/D1-0 = "0". An independent setting for the increment or decrement of the address counter can be made to the upper (AD15-8) and the lower (AD7-0) bits of the address. The address transition direction when data are written to GRAM is set with AM bits. AM: Set the direction of updating address counter automatically after data are written to GRAM. When AM = "0", the address counter is updated in the horizontal direction. When AM = "1", the address counter is updated in the vertical direction. When the window address is specified, data are written to the GRAM area specified by the window address in the manner specified with I/D1-0, AM bits.
Rev.0.22, May.23.2003, page 34 of 159
HD66787
TRI DFM1 DFM0
Preliminary
8-bit interface data format
First transmission
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
Second transmission
DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
0
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
0 1
* 0
* *
First transmission
Setting disabled Setting disabled
Second transmission Third transmission
DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12
1
1
0
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
First transmission
Second transmission
Third transmission
DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12 DB17 DB16 DB15 DB14 DB13 DB12
1
1
1
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
8-bit interface data format
I/D1-0="00" horizontal : decrement vertical : decrement
0000h
I/D1-0="01" horizontal : increment vertical : decrement
0000h
I/D1-0="10" horizontal : decrement vertical : increment
0000h
I/D1-0="11" horizontal : increment vertical : increment
0000h
AM="0" horizontal
EFAFh 0000h 0000h EFAFh 0000h EFAFh 0000h EFAFh
AM="1" vertical
EFAFh EFAFh EFAFh EFAFh
Note : Data are written only on the GRAM area specified with the window addresses when window addresses are set.
Address transition direction LG2-0: Rewrite data to GRAM after comparing the data that are written by the microcomputer to GRAM with the values in the compare registers (CP17-0) and performing logical operation. For details, see the "Graphics Operation Function" CP17-0: Set the value for the compare register, with which the data read out from GRAM or data written to GRAM by the microcomputer are compared. This function is not available with the external display interface mode. In the external display interface mode, make sure LG2-0 = "000". BGR: Reverse the order from R, G, B to B, G, R to the 18-bit data to write to GRAM. When setting BGR = 1, CP17-0 and WM17-0 bits will be automatically changed to the same effect.
Rev.0.22, May.23.2003, page 35 of 159
HD66787
18 bits Write data to GRAM Note 1) 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0
Preliminary
Conversion between RGB and BGR (BGR)
Logical/compare operation (LG2-0)
Logical operation (write data) LG2-0 = 000: Replacement
Compare operation (with compare register) LG2-0 = 110: Replacement of matched write data LG2-0 = 111: Replacement of unmatched write data
Write data to GRAM (WM17-0) Note 2)
Write data mask (WM17-0)
GRAM
Note 1) Data write to GRAM is executed by 18 bits. Logical operation is also executed by 18 bits. As to the assignment of bits, see the description regarding each bit data bus interface. Note 2) Write data mask (WM17-0) is set with the RAM write data mask register.
Logic/Compare Operation Display Control 1 (R07h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 PT1 IB8 IB7 0 IB6 0 IB5 0 IB4 DTE IB3 CL IB2 REV IB1 D1 IB0 D0
PT0 VLE2 VLE1 SPT
PT1-0: Determine the kind of source output in a non-display area in the partial display mode. For details, see the "Screen-split Drive function" section. PT1-0 bits
Source Output for Non-display Area PT1 0 0 1 1 PT0 0 1 0 1 Positive Polarity V31 V31 GND High impedance Negative Polarity V0 V0 GND High impedance
VLE2-1: When VLE1 = 1, the first screen is scrolled in the vertical direction. When VLE2 = 1, the second screen is scrolled in the vertical direction. The first and second screens cannot be scrolled simultaneously. This function is not available with the external display interface mode. In this case, make sure VLE2-1 = 0.
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HD66787 VLE Bits
VLE2 0 0 1 1 VLE1 0 1 0 1 Image on 2nd Screen Stationary Stationary Scrolled Setting disabled Image on 1st Screen Stationary Scrolled Stationary Setting disabled
Preliminary
CL: When CL = 1, 8-color display mode is selected. For details, see the "8-Color Display Mode" section. CL Bit
CL 0 1 Colors 262,144 8
SPT: When SPT = 1, liquid crystal is driven with 2 split screens. For details, see the "Screen Split Drive Function" section. This function is not available in the external display interface mode. In this case, make sure SPT = 0. REV: When REV = 1, a reverse display is shown. Inverting the grayscale levels allows the display of same data on both normally white and normally black panels. The source output during front, back porch periods and blank periods during the 2-split-screen display is made in accordance with settings with PT1-0 bits. Source Output in the Display Area
Source Output in the Display Area* REV GRAM Data 18'h00000 0 18'h3FFFF 18'h00000 1 18'h3FFFF V31 V0 Note: The output on the source lines during the front and back porch periods and blanking of the partial display is determined with PT1-0 bits. V0 V0 V31 V31 Positive Polarity V31 Negative Polarity V0
Rev.0.22, May.23.2003, page 37 of 159
HD66787 DTE: When DTE = 0, the DISPTMG output is fixed to GND. DTE Bit
DTE 0 1 DISPTMG Output Halt (GND) Operation (Vcc/GND)
Preliminary
D1-0: The graphics display is on when D1 = 1, and off when D1 = 0. When setting D1 = 0, the data are retained in GRAM. This means the graphics is instantly redisplayed when setting D1 to 1. When D1 is 0 (i.e., the display is off) all the source outputs are set to the GND level. This reduces the charged/discharged current on LCD, accompanied by the liquid crystal AC drive. When D1-0 = 01, the HD66787 continues the internal display operation, even while the external display is off. When D1-0 = 00, both the internal display operations and the external display operation are halted. In combination with GON and DTE bits, D1-0 bits control ON/OFF of display. For details, see the "Instruction Setting Flow" section. D1-0
D1 0 0 1 1 D0 0 1 0 1 Source Output GND GND Unlit display Display HD67789 Internal Operations Halt Operate Operate Operate Gate-Driver Control Signals (CL1, FLM, and M) Halt Operate Operate Operate
Note 1) Data are written to GRAM from the microcomputer irrespective of the setting of D1-0 bits. Note 2) In the standby mode, D1-0 = "00". However, the D1-0 register setting before entering standby modes is retained.
Display Control 2 (R08h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 FP3 FP2 FP1 IB8 FP0 IB7 0 IB6 0 IB5 0 IB4 0 IB3 BP3 IB2 BP2 IB1 IB0
BP1 BP0
FP3-0/BP3-0: Make settings for blank periods (the front and back porches), which are placed at the beginning and end of the display. FP3-0 and BP3-0 bits specify the number of raster-rows for the front and back porch respectively. When making this setting, make sure: BP + FP = <16 raster-rows FP >= 2 raster-rows BP >= 2 raster-rows In the external display interface mode, the back porch (BP) starts on the falling edge of VSYNC signal,
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HD66787
Preliminary
followed by display operation. After displaying the number of raster-rows set with NL bits, the front porch starts. After the front porch, a blank period ensues until an input of next VSYNC signal. FP and BP
FP3 BP3 0 0 0 0 0 FP2 BP2 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 FP1 BP1 0 0 1 1 0 FP0 BP0 0 1 0 1 0 Number of lines for the Front Porch Number of lines for the Back Porch Setting disabled Setting disabled 2 3 4 12 13 14 Setting disabled
VSYNC Back porch Display area
Front porch
Note: The output timing to the LCD panels is delayed two rasterrows from the input of synchronization signal.
External display interface
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HD66787 BP3-0, FP3-0 Setting Set BP3-0, FP3-0 bits as follows each in the following operation modes.
Operation of internal clock RGB interface VSYNC interface FLD1-0 = 01 FLD1-0 = 11 BP>= 2 lines BP= 3 lines BP >= 2 lines BP >= 2 lines FP >= 2 lines FP = 5 lines FP >= 2 lines FP >= 2 lines
Preliminary
FP +BP <= 16 lines
FP +BP <= 16 lines FP +BP = 16 lines
Frame Cycle Control (R0Bh)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 0 IB6 0 IB5 0 IB4 0 IB3 IB2 IB1 IB0
NO1 NO0 SDT1 SDT0 EQ1 EQ0 DIV1 DIV0
RTN3 RTN2 RTN1 RTN0
RTN3-0: Set the 1H (1 raster-row) period. RTN Bits and Clock Cycles
RTN3 0 0 0 RTN2 0 0 0 RTN1 0 0 1 : 1 1 1 1 1 1 0 1 RTN0 0 1 0 Clock Cycles per Raster-row 16 17 18 : 30 31
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HD66787
Preliminary
DIV1-0: Set the division ratio of clocks for internal operations (DIV1-0). Internal operations are in synchronization with the clock, the frequency of which is divided according to the DIV1-0 setting. When changing the number of drive raster-rows, adjust the frame frequency too. For details, see "Frame Frequency Adjustment Function". DIV Bits and Division Ratio
Internal Operating Clock Frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8
DIV1 0 0 1 1
DIV0 0 1 0 1
Division Ratio 1 2 4 8
fosc = R-C oscillation frequency
Formula for the frame frequency fosc Frame frequency = Clock cycles per raster-row x division ratio x (Line + BP + FP) fosc: R-C oscillation frequency Line: number of drive raster-rows (NL bit) Division ratio: DIV bit Clock cycles per raster-row: RTN bit FP : the number of raster-rows in the front porch BP : the number of raster-rows in the back porch [Hz]
EQ1-0: Equalizing period is prolonged as the number of clocks specified with EQ1-0 bits. The equalization signal is output only with the alternating current. EQ Bits
Equalizing period EQ1 0 0 1 1 EQ0 0 1 0 1
Internal Operation (synchronized with the internal operating clock) RGB I/F Operation (synchronized with DOTCLK )
Not equalized 1 clock 2 clocks 3 clocks
Not equalized 8 clocks 16 clocks 24 clocks
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HD66787
Preliminary
SDT1-0: Determine the amount of delay for the source output from the falling edge of the gate output. SDT Bits
Delay Time for Source Signal SDT1 0 0 1 1 SDT0 0 1 0 1
Internal Operation (synchronized with the internal operating clock) RGB I/F Operation (synchronized with DOTCLK)
1 clock 2 clocks 3 clocks 4 clocks
8 clocks 16 clocks 24 clocks 32 clocks
Note 1) The amount of delay for the source output is measured from the falling edge of the CL1.
1H period CL1
1H period
M
Gn
Sn
EQ Source output delay equalizing period
Source output delay and equalize period
Note 1) In internal operation and VSYNC interface modes, the reference clock is the internal operating clock. In RGB interface modes, the reference clock is DOTCLK.
NO1-0: Specify the amount of non-overlap time for the gate output. NO Bits
Non-overlap time NO1 0 0 1 1 NO0 0 1 0 1
Internal Operation (synchronized with the internal operating clock) RGB I/F Operation (synchronized with DOTCLK)
0 clock 4 clocks 6 clocks 8 clocks
0 clock 32 clocks 48 clocks 64 clocks
Note 1) The amount of non-overlap time is defined from the falling edge of the CL1.
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HD66787
1H period CL1 1H period
Preliminary
Gn
Gn + 1
Non-overlap period
Non-overlap period
External Display Interface Control (R0Ch)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 IB8 RM IB7 0 IB6 0 IB5 IB4 IB3 0 IB2 0 IB1 IB0
DM1 DM0
RIM1 RIM0
RIM1-0: Specify the RGB I/F mode when RGB interface is selected. Specifically, this setting specifies the RGB interface mode when it is selected by the setting DM and RM bits. The setting must be made before the display operation through external display interface. Do not make a setting during display. RIM Bits
RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface Mode 18-bit RGB interface (one-time transfer/pixel) 16-bit RGB interface (one-time transfer/pixel) 6-bit RGB interface (three-time transfers/pixel) Setting disabled
Note 1) The instruction register setting is possible only through a system interface. Note 2) Data transmission and input of DOTCLK in the 6-bit RGB interface mode should be executed by RGB.
DM1-0:Specify the display operation mode. The interface through which display operation is executed is selected with DM1-0 bits. This setting enables switching between internal clock operation and external display interface. Switching within the external display interface modes (between RGB-I/F and VSYNCI/F) cannot be made.
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HD66787 DM Bits
DM1 0 0 1 1 DM0 0 1 0 1 Display Interface Internal clock operation RGB interface VSYNC interface Setting disabled
Preliminary
RM: Specify the interface for RAM accesses. RAM is accessible only through the interface specified with RM bit. When the display data is written through RGB-I/F, set RM = 1. The RM-bit setting can be made irrespective of the display operation mode. This means the display data can be updated through a system interface even during the display period through RGB interface by setting RM = 0. RM Bit
RM 0 1 Interface for RAM Access System interface/VSYNC interface RGB interface
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HD66787
Preliminary
Setting for external display interface control allows selecting an optimum interface for the kind of display as follows. When displaying a moving picture (RGB-I/F/VSYNC-I/F), the display data must be written in the high-speed mode (HWM = 1) which enables high-speed RAM access with low power consumption. Display state and interfaces
Display State Still pictures Moving pictures Rewrite still picture area while displaying moving pictures. Moving pictures Operation Mode Internal clock operation RGB interface (1) RGB interface (2) RAM Access (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) Display Operation Mode (DM1-0) Internal clock operation (DM1-0 = 00) RGB interface (DM1-0 = 01) RGB interface (DM1-0 = 01)
VSYNC interface
System interface (RM = 0)
VSYNC interface (DM1-0 = 10)
Note 1) The instruction register setting is made only through system interface. Note 2) Switching between RGB-I/F and VSYNC-I/F cannot be made. Note 3) The RGB-I/F mode settings is not changeable during RGB I/F operation. Note 4) For details on the transition flow between operation modes, see the "External Display Interface" section. Note 5) Use the high-speed write mode (HWM = 1) during the write operation in RGB-I/F and VSYNC-I/F modes.
Internal clock operation mode All display operations are controlled by signals generated by the internal clock in internal clock operation mode. All inputs through the external display interface are invalid. The internal RAM is accessible only through a system interface. RGB interface mode (1) Display operation is controlled by the frame synchronization clock (VSYNC), line synchronizing signal (VSYNC), and dot clock (DOTCLK) in the RGB interface mode. These signals must be supplied throughout the display operation in this mode. All display data are stored in the internal RAM, transmitted with PD17-0 bits by pixel. The combination with the high-speed write mode and window address function enables simultaneous display of both moving picture areas and the internal RAM area. The data are transmitted only when the screen is being updated, thereby reducing the overall data transmission to minimum. The periods of the front (FP) and back (BP) porches and the display period (NL) are automatically generated in the HD66782 by counting the clock of line synchronizing signal (HSYNC) in accordance to the frame synchronizing signal (VSYNC). Transmit pixel data with PD 17-0 bits in accordance with the setting specified above. RGB interface mode (2)
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HD66787
Preliminary
When RGB-I/F is selected, RAM data are changeable through the system interface. This write operation must be performed while display data are not being transmitted through the RGB-I/F (ENABLE = High). When reverting from the system interface mode to the data transmission through the RGB interface, make a new setting for the address set and index (R22h) after changing the aforementioned settings. VSYNC interface mode The internal display operation is synchronized with the frame-synchronizing signal (VSYNC) in the VSYNC interface mode. By writing data to RAM at a fixed speed on the falling edge of VSYNC, it enables moving pictures display with a system interface. In this case, there are some constraints in the RAM write speed and methods. For details, see the "External Display Interface" section. In the VSYNC-I/F mode, only VSYNC input is valid. Other input signals for the external display interface are invalid. The front porch (FP), back porch (BP) periods and display period (NL) are automatically generated in accordance to the frame synchronizing signal (VSYNC) according to the register setting of HD66787.
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HD66787 LTPS Interface Control (R0Dh)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 CLW CLW CLW 0 0 0 TG0 0 0 2 1 0 IB6 0 IB5 IB4 IB3 0 IB2 STG 2
Preliminary
IB1
IB0
SHW SHW 0 1
STG STG 1 0
The HD66787 enables connection to LTPS-TFT panels by outputting timing signals (CL1, SFTCLK) for controlling low-temperature poli-Si TFT (LTPS-TFT) panels with incorporated gates. For details, see the "Low-temperature Poli-Si TFT Control" section.
CL1
CLW2-0
SHW1-0 SFTCLK STG2-0
Note) SFTCLK is output under the same condition as CL1.
Timing signals for LTPS-TFT panels
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HD66787 STG2-0:Set the output position of the pulse of SFTCLK signal. STG2-0
STG 2 STG 1 STG 0 SFTCLK signal : pulse output position
internal operation (synchronized with the internal operating clock) RGB interface operation
Preliminary
(synchronized with DOTCLK)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 clock 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks
0 clock 8 clocks 16 clocks 24 clocks 32 clocks 40 clocks 48 clocks 56 clocks
Note 1) The number of clocks is counted from the falling edge of the CL1 signal.
SHW1-0: Set the width of the pulse of SFTCLK signal during "High". SHW1-0
SHW 1 SHW 0 SFTCLK signal : purse width during "High"
internal operation (synchronized with the internal operating clock) RGB interface operation (synchronized with DOTCLK)
0 0 1 1
0 1 0 1
1 clock 2 clocks 3 clocks 4 clocks
8 clocks 16 clocks 24 clocks 32 clocks
In making settings for SFTCLK signal, the following condition must be observed. STG2-0 + SHW1-0 8 clocks (Internal operation) 64 clocks (RGB interface operation)
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HD66787 CLW2-0: Set the width of the pulse of CL1 signal during "Low".
CLW 2 CLW 1 CLW 0 CL1 signal : pulse width during "Low"
internal operation (synchronized with the internal operating clock) RGB interface operation
Preliminary
(synchronized with DOTCLK)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks
8 clocks 16 clocks 24 clocks 32 clocks 40 clocks 48 clocks 56 clocks 64 clocks
Note 1) The number of clocks is counted from the falling edge of the CL1 signal.
TG0: Change the output timing of CL1 and SFTCLK signals. If TG0 =1, the setting in SHW is nullified and the frequencies of CL1 and SFTCLK become the frequency of normal mode divided by 2. The output timing of each signal is illustrated as follows.
FLM(TG0=1) t1 CL1(TG0=1) t2 t2
Timing of Internal Operation t1 = RTN - CLW t2 = STG t3 = SDT internal operation RGB-I/F t3 t3 First Line Second Line : 1H = 16clks : 1H = Number of DLTCLKs
SFTCLK(TG0=1)
Sn
CL1 and SFTCLK (TG0 = 1)
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HD66787
RTN FLM (TG0 = 0) CLW CL1 (TG0 = 0) STG SFTCLK (TG0=0) SDT S (n) 1st line 2nd line
Preliminary
FLM (TG0 = 1) RTN-CLW CL1 (TG0 = 1) STG SFTCLK (TG0=1 SDT S (n) 1st line 2nd line STG
FLM level-shift output (TG0=1)
CL1 level-shift output (TG0=1)
SFTCLK level-shift output (TG0=1)
CL1 and SFTCLK timing chart
Rev.0.22, May.23.2003, page 50 of 159
HD66787 Power Control 1 (R10h) Power Control 2 (R11h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 SAP2 SAP1 SAP0 0 0 0 0 IB8 IB7 0 IB6 IB5 IB4 AP0 IB3 0 IB2 DK
Preliminary
IB1
IB0
BT2 BT1 BT0
AP2 AP1
SLP STB
W
1
0
0
DC12 DC11 DC10
0
DC02 DC01 DC00
0
VC2 VC1 VC0
SAP2-0: Adjust the amount of fixed current from the fixed current source of operational amplifier for the source driver. When the amount of fixed current is set large, the operational amplifier will stabilize, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. During non-display operation, set SAP2-0 = "000" to halt the operation of operational amplifier, to reduce the current consumption. SAP Bits and the amount of current for the Op-amp
SAP2 0 0 0 0 SAP1 0 0 1 1 SAP0 0 1 0 1 Op-amp Current Halt Setting disabled 0.62 (fixed) 0.71 (fixed) SAP2 1 1 1 1 SAP1 0 0 1 1 SAP0 0 1 0 1 Op-amp Current 1 (fixed) 1.25 (fixed) 1.43 (fixed) Setting disabled
BT2-0: Change the step-up scale of the step-up circuit. Adjust the scale according to the voltage. Smaller scale consumes lesser current. DC02-00: Select the operating frequency for the step-up circuit 1. The higher frequency enhances the drive capacity of step-up circuit as well as the display quality, while the current consumption will increase. Adjust the frequency taking both the display quality and the current consumption into consideration. DC12-10: Select the operating frequency for the step-up circuit 2. The higher frequency enhances the drive capacity of step-up circuit as well as the display quality, while the current consumption will increase. Adjust the frequency taking both the display quality and the current consumption into consideration. AP2-0: Adjust the amount of fixed current from the fixed current source of operational amplifier for the liquid crystal drive power supply. When the amount of fixed current is set large, the liquid crystal drive capacity will be enhanced and the display quality will improve, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. During non-display operation, set AP2-0 = "000" to halt the operation of operational amplifier to reduce current consumption. DK: Control the operation of the step-up circuit 1. When turning on the power supply, stop the start up of VLOUT1 for a moment, and wait for an enough time until VLOUT2 is stabilized before starting up VLOUT1. For details, see the "Power Supply Setting Flow" section.
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HD66787
Preliminary
SLP: When SLP = 1, the HD66789 enters into the sleep mode. In the sleep mode, internal display operation is halted except the R-C oscillator to reduce current consumption. Only power control instructions (BT2-0, DC2-0, AP2-0, SLP, STB, VC2-0, VRH4-0, VCOMG, VDV4-0, and VCM4-0 bits) are executed during the sleep mode. No change is made to the GRAM data or instructions during the sleep mode, although it is retained. STB: When STB = 1, the HD66789 enters into the standby mode. In the standby mode, display operation is completely halted, and all internal operation including the internal R-C oscillator and reception of external clock pulse, is halted. For details, see the "Standby Mode" section. Only instructions to release the standby mode (STB = 0) and to start oscillation are accepted during the standby mode. Changes in the GRAM data or instructions during the standby mode are susceptible to destruction. These changes should be made after releasing the standby mode. VC2-0: Adjust the reference voltage for VREG1OUT, VciOUT voltages to the optimum ratio of Vci.
AP2 0 0 0 0 1 1 1 1
AP1 0 0 1 1 0 0 1 1
AP0 0 1 0 1 0 1 0 1
Amount of current in operational amplifier halt setting disabled 0.5 (fixed) 0.75 (fixed) 1 (fixed) 1.25 (fixed) 1.5 (fixed) setting disabled
DC02 0 0 0 0 1 1 1 1
DC01 0 0 1 1 0 0 1 1
DC00 0 1 0 1 0 1 0 1
Step-up circuit 1 step-up frequency oscillation clock / 8 oscillation clock / 16 oscillation clock / 32 oscillation clock / 64 oscillation clock / 128 setting disabled setting disabled setting disabled
DC12 0 0 0 0 1 1 1 1
DC11 0 0 1 1 0 0 1 1
DC10 0 1 0 1 0 1 0 1
Step-up circuit 2 step-up frequency oscillation clock / 16 oscillation clock / 32 oscillation clock / 64 oscillation clock / 128 oscillation clock / 256 setting disabled setting disabled setting disabled
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HD66787
BT2 BT1 BT0 VLOUT1 output (DDVDH) Vci1 x 2 [x2] * * * * * * * * * * * * * VLOUT4 output (VCL) Vci1 x -1 [x-1] * VLOUT2 output (VGH) DDVDH x 3 [x 6] DDVDH x 3 [x 6] DDVDH x 3 [x 6] Vci1 +DDVDH x 2 [x 5] Vci1 +DDVDH x 2 [x 5] Vci1 +DDVDH x 2 [x 5] DDVDH x 2 [x 4] DDVDH x 2 [x 4]
Preliminary
VLOUT3 output (VGL) - (Vci1+DDVDH x 2) [x -5] - (DDVDH x 2) [x -4] - (Vci1+DDVDH) [x -3] - (Vci1+DDVDH x 2) [x -5] - (DDVDH x 2) [x -4] - (Vci1+DDVDH) [x -3] - (DDVDH x 2) [x -4] - (Vci1+DDVDH) [x -3] Capacitor connection pins
DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21, C22, DDVDH, VGH, VGL, VCL, C11, C12, C21
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Note 1) The numerals in the bracket [ ] show the step-up scale from Vci1. Note 2) The capacitor connection pins are step-up capacitors which are necessary for DDVDH, VCL, VGH, VGL voltages. Note 3) Set the voltage within the following range: DDVDH = 5.5 V (Max.), VCL = - 3.3 V (Min.), VGH = 16.5 V (Max.), VGL = -16.5 V (Min.)
VC2 0 0 0 0 1 1 1 1
VC1 0 0 1 1 0 0 1 1
VC0 0 1 0 1 0 1 0 1
VciOUT output voltage (REGP) Vci 0.92 x Vci 0.87 x Vci 0.83 x Vci 0.76 x Vci 0.73 x Vci setting disabled setting disabled
DK 0 1
Operation of step-up circuit 1 Operation Halt
Rev.0.22, May.23.2003, page 53 of 159
HD66787 Power Control 3 (R12h) Power Control 4 (R13h)
Preliminary
R/W W W
RS 1 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 0 0
IB8 0
IB7 0 0
IB6 0 0
IB5 0 0
IB4
IB3
IB2
IB1
IB0
PON VRH3 VRH2 VRH1 VRH0
VCM4 VCM3 VCM2 VCM1 VCM0
VCO VDV4 VDV3 VDV2 VDV1 VDV0 MG
PON: Start operation of VLOUT3. To stop operation, set PON = 0. To start operation, set PON = 1. VRH3-0: Set the scale for amplifying VLOUT1 voltage (the reference voltage for VCOM and grayscale voltage). REGP voltage is amplified by 1.33 ~ 2.775 times. VCOMG: When VCOMG = 1, VcomL outputs a negative voltage (1.0V ~ -Vci+0.5V Max.). When VCOMG = 0, the amplifiers for the negative voltage is halted, thereby saving power consumption. When VCOMG = 0, settings with VDV4-0 bits are invalid. In this case, to adjust AC amplitude of Vcom, make settings with VCM4-0 bits (VcomH setting). VCOMG = 1 is valid when PON = 1. VDV4-0: Set the AC amplitude of Vcom during Vcom AC drive. The amplitude can be specified within the range of 0.6 ~ 1.23 times of VREG1OUT. When VCOMG = 0, this setting is invalid. VCM4-0: Set the VcomH voltage (The higher voltage during Vcom AC drive). The voltage can be specified within the range of 0.4 ~ 0.98 times of VREG1OUT. When VCM4-0 = "11111", the internal volume adjustment operation is halted, and the VcomH voltage can be adjust by placing an external resistor from VcomR.
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HD66787
VRH3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VRH2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VRH1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VRH0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VREG1OUT voltage REGP x 1.33 REGP x 1.45 REGP x 1.55 REGP x 1.65 REGP x 1.75 REGP x 1.80 REGP x 1.85 halt REGP x 1.90 REGP x 2.175 REGP x 2.325 REGP x 2.475 REGP x 2.625 REGP x 2.700 REGP x 2.775 halt
Preliminary
Rev.0.22, May.23.2003, page 55 of 159
HD66787
VCM4 VCM3 VCM2 VCM1 VCM0
Preliminary
VcomH VREG1OUT x 0.40 VREG1OUT x 0.42 VREG1OUT x 0.44 : VREG1OUT x 0.64 VREG1OUT x 0.66 VREG1OUT x 0.68
Halt internal volume. Adjust with a variable external resistor from VcomR.
VDV4 VDV3 VDV2 VDV1 VDV0
Vcom amplitude VREG1OUT x 0.60 VREG1OUT x 0.63 VREG1OUT x 0.66 : VREG1OUT x 0.96 VREG1OUT x 0.99 VREG1OUT x 1.02
Setting disabled
0 0 0 : 0 0 0 0
0 0 0 : 1 1 1 1
0 0 0 : 1 1 1 1
0 0 1 : 0 0 1 1
0 1 0 : 0 1 0 1
0 0 0 : 0 0 0 0
0 0 0 : 1 1 1 1
0 0 0 : 1 1 1 1
0 0 1 : 0 0 1 1
0 1 0 : 0 1 0 1
1 1 1 : 1 1 1 1
0 0 0 : 1 1 1 1
0 0 0 : 1 1 1 1
0 0 1 : 0 0 1 1
0 1 0 : 0 1 0 1
VREG1OUT x 0.70 VREG1OUT x 0.72 VREG1OUT x 0.74 : VREG1OUT x 0.94 VREG1OUT x 0.96 VREG1OUT x 0.98
Halt internal volume. Adjust with a variable external resistor from VcomR.
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 *
0 0 1 1 0 0 1 1 *
0 1 0 1 0 1 0
VREG1OUT x 1.05 VREG1OUT x 1.08 VREG1OUT x 1.11 VREG1OUT x 1.14 VREG1OUT x 1.17 VREG1OUT x 1.20 VREG1OUT x 1.23
Setting disabled
*
Setting disabled
Note 1) Adjust VREG1OUT and VCM0-4 to set VcomH the same level as VDH or less. Note 2) Adjust VREG1OUT and VDV0-4 to set the amplitude of Vcom 6.0V or less.
RAM Address Set (R21h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 AD 15 AD 14 AD 13 AD 12 AD 11 AD 10
IB9 AD 9
IB8 AD 8
IB7 IB6 AD 7 AD 6
IB5 AD 5
IB4 AD 4
IB3 IB2 AD 3 AD 2
IB1 AD 1
IB0 AD 0
AD15-0: Make the initial setting for the GRAM address in the address counter (AC). After GRAM data are written, the address counter is automatically updated according to the settings with AM, I/D bits and the setting for a new GRAM address is not required in the address counter. Therefore, data are written consecutively without resetting the address. The address counter is not automatically updated when data are read out from GRAM. GRAM address setting can not be made during the standby mode. An address set should be made within the area specified with the window address. When the RGB interface is selected (RM = 1), the setting of the address for AD15-0 is made every frame at the falling edge of VSYNC. When the internal clock operation or VSYNC interface is selected (RM = 0), the setting of the address is made when the instruction is executed.
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HD66787 GRAM Address Range
AD15-AD0 "0000"H - "00AF"H "0100"H - "01AF"H "0200"H - "02AF"H "0300"H - "03AF"H : "EC00"H - "ECAF"H "ED00"H - "EDAF"H "EE00"H - "EEAF"H "EF00"H - "EFAF"H GRAM Setting Bitmap data for G1 Bitmap data for G2 Bitmap data for G3 Bitmap data for G4 : Bitmap data for G237 Bitmap data for G238 Bitmap data for G239 Bitmap data for G240
Preliminary
Write Data to GRAM (R22h)
R/W W RS 1
RAM write data (WD17-0) The pin assignment for DB17-0 varies for each interface (see below).
PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6
RGB-I/F mode:
PD5 WD 5
PD4 WD 4
PD3 PD2 PD1 PD0 WD WD 2 3 WD 1 WD 0
WD 17
WD WD 16 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD17-0: All data are expanded into 18 bits internally before written to GRAM. Each interface has its own way of expanding data to 18 bits. The grayscale level is selected according to the GRAM data. The address is automatically updated according to the setting with the AM and I/D bits after data are written to GRAM. During the standby mode, no access is allowed to GRAM. When 8 or 16 bit interface modes is selected, the data in the MSB of R and B pixels are also written to the LSB of R and B pixels respectively to expand the 8/16- bit data into the 18bit data internally. During the RGB interface mode, when writing data to RAM through a system interface, make sure to avoid conflicts between writing through the RGB interface and writing through the system interface. When the 18-bit RGB interface is selected, the18-bit data in PD17-0 bits are written, and 262,144 colors are available. When the 16-bit RGB interface is selected, the data in the MSB of R and B pixels are also written to the LSB of R and B pixels respectively, and 65,536 colors are available.
Rev.0.22, May.23.2003, page 57 of 159
HD66787
18-bit interface(262,144 colors)
INPUT DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
Preliminary
DB 0
Write Data to GRAM
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
16-bit interface(65,536 colors)
INPUT DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
Write Data to GRAM
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
9-bit interface (262,144 colors)
1st Transmission (Upper) INPUT DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 2nd Transmission (Lower) DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9
Write Data to GRAM
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
Write data to GRAM: Bit assignment
Rev.0.22, May.23.2003, page 58 of 159
HD66787
8-bit interface (65,536 colors) TRI = 0, DFM1-0 = 00
1st Transmission (Upper) INPUT DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 2nd Transmission (Lower) DB 15 DB 14 DB 13 DB 12 DB 11 DB 10
Preliminary
Write Data to GRAM
WD 17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
8-bit interface (262,144 colors) TRI =1, DFM1-0 = 10
1st Transmission INPUT DB DB DB DB DB DB DB 17 16 15 14 13 12 17 2nd Transmission DB 16 DB DB 15 14 DB DB 13 12 3rd Transmission DB DB DB 17 16 15 DB DB 14 13 DB 12
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
8-bit interface (65,536 colors) TRI =1, DFM1-0 = 11
1st Transmission INPUT DB DB DB DB DB DB DB 17 16 15 14 13 12 17 2nd Transmission DB 16 DB DB 15 14 DB DB 13 12 3rd Transmission DB DB DB 17 16 15 DB DB 14 13 DB 12
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Write data to GRAM: Bit assignment
Rev.0.22, May.23.2003, page 59 of 159
HD66787
18-bit RGB interface (262,144 colors)
INPUT PD PD PD PD PD PD 17 16 15 14 13 12 PD 11 PD 10 PD PD 9 8 PD PD 7 6 PD 5 PD 4 PD 3 PD PD 2 1 PD 0
Preliminary
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel The index register should be set when data is written in RGB-I/F mode.
16-bit RGB interface (65,563 colors)
INPUT PD PD PD PD PD 17 16 15 14 13 PD PD 11 10 PD PD 9 8 PD PD 7 6 PD 5 PD PD 4 3 PD PD 2 1
Write Data to GRAM
WD WD WD WD WD 17 16 15 14 13
WD WD WD WD WD WD WD WD WD WD WD 11 10 9 8 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel The index register should be set when data is written in RGB-I/F mode.
6-bit RGB interface (262,144 colors)
1st Transmission INPUT PD PD PD PD PD PD PD 17 16 15 14 13 12 17 2nd Transmission PD 16 PD PD 15 14 PD PD 13 12 3rd Transmission PD PD PD PD PD 17 16 15 14 13 PD 12
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel The index register should be set when data is written in RGB-I/F mode.
Write data to GRAM (RGB interface): Bit assignment
Rev.0.22, May.23.2003, page 60 of 159
HD66787
GRAM data settings
Preliminary
Grayscale Negative V0 (V0-V1)/2 V1 (V1-V2)/2 V2 (V2-V3)/2 V3 (V3-V4)/2 V4 (V4-V5)/2 V5 (V5-V6)/2 V6 (V6-V7)/2 V7 (V7-V8)/2 V8 (V8-V9)/2 V9 (V9-V10)/2 V10 (V10-V11)/2 V11 (V11-V12)/2 V12 (V12-V13)/2 V13 (V13-V14)/2 V14 (V14-V15)/2 V15 (V15-V16)/2 Positive V31 (V30-V31)/2 V30 (V29-V30)/2 V29 (V28-V29)/2 V28 (V27-V28)/2 V27 (V26-V27)/2 V26 (V25-V26)/2 V25 (V24-V25)/2 V24 (V23-V24)/2 V23 (V22-V23)/2 V22 (V21-V22)/2 V21 (V20-V21)/2 V20 (V19-V20)/2 V19 (V18-V19)/2 V18 (V17-V18)/2 V17 (V16-V17)/2 V16 (V15-V16)/2
GRAM data settings
Grayscale Negative V16 (V16-V17)/2 V17 (V17-V18)/2 V18 (V18-V19)/2 V19 (V19-V20)/2 V20 (V20-V21)/2 V21 (V21-V22)/2 V22 (V22-V23)/2 V23 (V23-V24)/2 V24 (V24-V25)/2 V25 (V25-V26)/2 V26 (V26-V27)/2 V27 (V27-V28)/2 V28 (V28-V29)/2 V29 (V29-V30)/2 V30 (V30-V31)/2 (V30-V31)/3 V31 Positive V15 (V14-V15)/2 V14 (V13-V14)/2 V13 (V12-V13)/2 V12 (V11-V12)/2 V11 (V10-V11)/2 V10 (V9-V10)/2 V9 (V8-V9)/2 V8 (V7-V8)/2 V7 (V6-V7)/2 V6 (V5-V6)/2 V5 (V4-V5)/2 V4 (V3-V4)/2 V3 (V2-V3)/2 V2 (V1-V2)/2 V1 (V0-V1)/2 (V0-V1)/3 V0
RGB 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111
RGB 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111
GRAM data and LCD output level
Rev.0.22, May.23.2003, page 61 of 159
HD66787 RAM Access through RGB-I/F and System I/F
Preliminary
The HD66787 writes all display data on the panels to the internal RAM. This enables the transfer of only the data for the moving picture area as well as for the frames for updating screens through the RGB interface. By writing data in the high speed write mode (HWM = 1) and with the window address function, the HD66787 enables the high-speed access to RAM with low power consumption while displaying moving pictures. In the frames other than the moving picture screen update, the display data in the area other than the moving picture area can be updated through a system interface. The RAM access is also possible through a system interface even in the RGB-I/F mode. In the RGB interface mode, data are written to RAM in synchronization with the DOTCLK during ENABLE = "Low". When writing data in the RGB-I/F mode through the system interface, it is necessary to set the ENABLE "High" to stop writing through the RGB interface. After accessing to RAM through the system interface, wait an enough time for the write/read bus cycle before starting accessing to RAM through the RGB interface. When RAM accesses through the RGB and system interfaces conflict, there will be no guarantee that data are properly written to RAM.
Updating (both panels) Updating (both panels)
VSYNC ENABLE DOTCLK PD17-0
Setting of index System interface
Index R22 RM=0 Setting of address Index R22 Updating of area other than moving picture area RM=1 Setting of address Index R22
Updating or moving picture area
Updating still picture area*1
Updating or moving picture area
Note 1) When RGB-I/F is selected, the address setting is made at every falling edge of VSYNC. Note 2) The address set and the index set must be made before the RAM access throught the RGB interface. Note 3) The high-speed write mode should be used in RGB-I/F and VSYNC-I/F modes.
2001/01/01 00:00 Still picture area
Moving picture area
Updating Still Picture Area during Displaying a Moving Picture
Rev.0.22, May.23.2003, page 62 of 159
HD66787 Read Data Read from GRAM (R22h)
R/W R RS 1
Preliminary
RAM Read data (RD17-0) The pin assignment for DB17-0 varies for each interface (see below).
RD17-0: Read 18-bit data from GRAM. The bit assignment for the data that are read out from GRAM is different according to the interface. When data are read out from GRAM to the microcomputer, the first word read immediately after GRAM address set are latched in the internal read-data latch, and thereby nullify the data in the data bus (DB17-0). The second word is read as valid data. When the HD66787 performs an internal bit processing, such as logical operation, it uses the data latched in the read-data latch. Therefore the processing is completed by single read out operation. The data are expanded internally into 18 bits before going through the logical operation. When the 8-/16-bit interfaces are selected, the GRAM data in the LSBs of R and B pixels are not read out. This function is not available in RGB interface mode.
18-bit interface
GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
One pi xel
Read data
RD RD RD RD 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
RD RD RD RD 6 5 4 3
RD RD RD 2 1 0
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB DB 8 7
DB 6
DB 5
DB DB 4 3
DB 2
DB 1
DB 0
Read data from GRAM: Bit assignment
Rev.0.22, May.23.2003, page 63 of 159
HD66787
16-bit interface
GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1
Preliminary
B0
One pixel
Read RD RD RD RD data 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
RD RD RD RD 6 5 4 3
RD RD RD 2 1 0
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
9-bit interface
GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
One pixel
Read data
RD RD RD RD 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
RD RD RD RD 6 5 4 3
RD RD RD 2 1 0
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB DB 9 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 9
1st Transmission (Upper)
2nd Transmission (Lower)
8-bit interface / SPI
GRAM data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Read data
RD RD RD RD 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
RD RD RD RD 6 5 4 3
RD RD RD 0 2 1
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
1st Transmission (Upper)
2nd Transmission (Lower)
Read data from GRAM: Bit assignment
Rev.0.22, May.23.2003, page 64 of 159
HD66787
Preliminary
Set the I/D, AM, HSA/HSE, and VSA/VEA bits
Set the I/D, AM, HSA/HSE, and VSA/VEA bits
Address: N set
Address: N set
First word
Dummy read (invalid data) GRAM Read-data latch
First word
Dummy read (invalid data) GRAM Read-data latch
Second word
Read (data of address n) Read-data latch DB17-0
Second word
Write (data of address n) DB17-0 GRAM
Address: M set
Automatic address update: N +
First word
Dummy read (invalid data) GRAM Read-data latch
First word
Dummy read (invalid data) GRAM Read-data latch
Second word
Read (data of address n) Read-data latch DB17-0
Second word
Write(data of address n) DB17-0 GRAM
i) Read data to the microcomputer
ii) Logical arithmetic operation inside HD66787
GRAM read sequence
Rev.0.22, May.23.2003, page 65 of 159
HD66787 RAM Write Data Mask (R23h) RAM Write Data Mask (R24h)
Preliminary
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0
IB8
IB7 0 0
IB6 0 1
IB5
IB4
IB3
IB2
IB1
IB0
WM WM WM WM WM WM 11 10 9 8 7 6 0 0 0 1 1 1
WM WM 5 4
WM WM WM WM 3 2 1 0
W
1
WM WM WM WM WM WM 17 16 15 14 13 12
WM17-0: Write-mask the data when these data are written to GRAM by bit. For example, if WM17 = 1, the WM17 write-mask the MSB of the data to write to GRAM so that the data in the MSB are not written to GRAM. The rest of WM16-0 bits also write-mask the data in the corresponding bits when these bits are set to "1". For details, see the "Graphics Operation Function" section. The WM17-0 bits write-mask the data to write to GRAM, which are expanded, if necessary, into 18 bits. This function is not available in the RGB-I/F mode.
Write mask
WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
RAM write data mask
Rev.0.22, May.23.2003, page 66 of 159
HD66787 Control (R30h to R39h)
R/W R30 R31 R31 R33 R34 R35 R36 R37 R38 R39 W 1 0 0 0 W W W W W RS 1 1 1 1 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB8 IB7 IB6 0 0 0 0 0 0 0 0 0 0 IB5 0 0 0 0 0 IB4 0 0 0 0 0 IB3 0 0 0 0 0 IB2
Preliminary
IB1 IB0
PKP PKP PKP 12 11 10 PKP PKP PKP 32 31 30 PKP PKP PKP 52 51 50 PRP PRP PRP 12 11 10 PKN PKN PKN 12 11 10 PKN PKN PKN 32 31 30 PKN PKN PKN 52 51 50 PRN PRN PRN 12 11 10
PKP PKP PKP 02 01 00 PKP PKP PKP 22 21 20 PKP PKP PKP 42 41 40 PRP PRP PRP 02 01 00 PKN PKN PKN 02 01 00 PKN PKN PKN 22 21 20 PKN PKN PKN 42 41 40 PRN PRN PRN 02 01 00
W W W
1 1 1
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
W
1
0
0
0
VRP VRP VRP VRP VRP 14 13 12 11 10 VRN VRN VRN VRN VRN 11 10 14 13 12
0
0
0
0
VRP VRP VRP VRP 03 02 01 00 VRN VRN VRN VRN 03 02 01 00
0
0
0
0
Control Instructions PKP52-00 PRP12-00 PKN52-00 PRN12-00 VRP14-00 VRN14-00 : The fine adjustment registers for positive polarity. : The gradient adjustment registers for positive polarity. : The fine adjustment registers for negative polarity. : The gradient adjustment registers for negative polarity. : The amplitude adjustment registers for positive polarity. : The amplitude adjustment registers for negative polarity.
For details, see the " adjustment" section.
Rev.0.22, May.23.2003, page 67 of 159
HD66787 Vertical Scroll Control (R41h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 0 0 0 0 0 0 IB9 0 IB8 0 IB7 IB6 IB5 IB4 IB3
Preliminary
IB2
IB1
IB0
VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL0
VL7-0: Specify the number of raster-rows that are scrolled and control smooth scrolling in the vertical direction. The number of raster-rows is specified between 0 to 240. The raster-rows of the specified number are being scrolled during display. When the 240th raster-row is displayed, the scrolling display starts afresh from the 1st raster-row. The number of raster-rows that are scrolled (VL7-0) can be specified when the first panel vertical scroll enable bit VLE1 = 1 or the second panel vertical scroll enable bit VLE2 = 1. The number of raster-rows is fixed (not changeable) when VLE2-1 = 00. This function is not available in the external display interface mode. VL Bits and Display-start Raster-row
VL7 0 0 0 . . 1 1 VL6 0 0 0 . . 1 1 VL5 0 0 0 . . 1 1 VL4 0 0 0 . . 0 0 VL3 0 0 0 . . 1 1 VL2 0 0 0 . . 1 1 VL1 0 0 1 . . 1 1 VL0 0 1 0 . . 0 1 Amount of Scrolling (Number of raster-row) 0 raster-row 1 raster-row 2 raster-rows . . 238 raster-rows 239 raster-rows
Note: When setting the number of raster-rows for scrolling, it must be 239 or less.
1st-Screen Drive Position (R42h) 2nd-Screen Drive Position (R43h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10 IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10 SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
W
1
SS17-10: Specify the start position for driving the first screen by line. The liquid crystal is driven by from the gate driver of "the set value + 1". SE17-10: Specify the end position for driving the first screen by line. The liquid crystal is driven by to the gate driver of "the set value + 1". For instance, when SS17-10 = "07"H and SE17-10 = "10"H, the liquid crystal is driven from G8 to G17, and black display is driven from G1 to G7, and G18 thereafter. Make sure that SS17-10 SE17-10 "EF"H. For details, see the "Screen Split Drive Function" section.
Rev.0.22, May.23.2003, page 68 of 159
HD66787
Preliminary
SS27-20: Specify the start position for driving the second screen by line. The liquid crystal is driven by from the gate driver of "the set value + 1". The second screen is driven when SPT = 1. SE27-20: Specify the end position for driving the second screen by line. The liquid crystal is driven by to the gate driver of "the set value + 1". For instance, when SPT = 1, and SS27-20 = "20"H, SE27-20 = "4F"H, the liquid crystal is driven from G33 to G80. Make sure that SS17-10 SE17-10 < SS27-20 SE27-20 "EF"H. For details, see the "Screen Split Drive Function" section. Horizontal RAM Address Position (R44h) Vertical RAM Address Position (R45h)
R/W W
RS 1
IB15 IB14 IB13 IB12 IB11 IB10
IB9
IB8
IB7
IB6
IB5
IB4
IB3
IB2
IB1
IB0
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
W
1
HSA7-0/HEA7-0: Specify the start/end positions of the window-address range in the horizontal direction by address. Data are written to GRAM within the area determined by the addresses specified by HEA7-0 and HSA7-0. These addresses must be set before RAM write. In setting these bits, make sure that "00"h HSA7-0 HEA7-0 "AF"h. VSA7-0/VEA7-0: Specify the start/end positions of the window-address range in the vertical direction by address. Data are written to GRAM within the area determined by the addresses specified by VEA7-0 and VSA7-0. These addresses must be set before RAM write. In setting these bits, make sure that "00"h VSA7-0 VEA7-0 "EF"h.
HSA
0000h
HEA
VSA
Window Address
Window address setting area "00"h=< HSA7-0=VEA
GRAM address space
EFAFh
Note 1) The window address area is set within the GRAM address space. Note 2) In the high-speed write mode, data are written to the GRAM every four words. Therefore, depending on the window address setting, dummy write operations are required. For details, see the "High-Speed Burst RAM Write Function" section. Note 3) The address set must be within the window address area. In the high-speed write mode, dummy write area must also be within the window address area.
GRAM address area and window-address range
Rev.0.22, May.23.2003, page 69 of 159
HD66787
Preliminary
Instruction List
Upper Index SR 0* Main Category Upper Index Index Status Read Display Control Sub Category Command Index Status Read Oscillation Start Device Code Read Driver Output Control LCD AC driving Control Entry Mode Compare Register (1) Compare Register (2) Setting Disabled Display Control (1) Display Control (2) Setting Disabled Setting Disabled Frame Cycle Adjustment Control External Display Interface Control LTPS Interface Control Setting Disabled Setting Disabled Power Control (1) Power Control (2) Power Control (3) Power Control (4) Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled RAM Address Set RAM data Write/Read RAM Write Data Mask (1) RAM Write Data Mask (2) Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled 0 0 AD15 (0) AD14 (0) AD13 (0) AD12 (0) AD11 (0) AD10 (0) AD9 (0) AD8 (0) AD7 (0) AD6 (0) AD5 (0) AD4 (0) AD3 (0) AD2 (0) AD1 (0) AD0 (0) 0 0 0 0 SAP2 (0) 0 0 0 SAP1 (0) 0 0 SAP0 (0) 0 0 0 0 0 VDV3 (0) BT2 (0) DC12 (0) 0 VDV2 (0) BT1 (0) DC11 (0) 0 VDV1 (0) BT0 (0) DC10 (0) 0 VDV0 (0) 0 0 0 0 AP2 (0) DC02 (0) 0 0 AP1 (0) DC01 (0) 0 0 AP0 (0) DC00 (0) PON (0) VCM4 (0) 0 0 VRH3 (0) VCM3 (0) DK (1) VC2 (0) VRH2 (0) VCM2 (0) SLP (0) VC1 (0) VRH1 (0) VCM1 (0) STB (0) VC0 (0) VRH0 (0) VCM0 (0) 0 0 0 0 0 0 PT1 (0) 0 PT0 (0) FP3 (1) VLE2 (0) FP2 (0) VLE1 (0) FP1 (0) SPT (0) FP0 (0) 0 0 0 0 0 0 DTE (0) 0 CL (0) BP3 (1) REV (0) BP2 (0) D1 (0) BP1 (0) D0 (0) BP0 (0) IB15 * L7 * 0 0 0 TRI (0) 0 0 IB14 * L6 * 0 VSPL (0) 0 DFM1 (0) 0 0 IB13 * L5 * 0 HSPL (0) 0 DFM0 (0) CP11 (0) 0 Upper Code IB12 * L4 * 0 DPL (0) 0 BGR (0) CP10 (0) 0 IB11 * L3 * 0 EPL (0) 0 0 CP9 (0) 0 IB10 * L2 * 1 0 1 0 CP8 (0) 0 IB9 * L1 * 1 0 B/C (0) HWM (0) CP7 (0) 0 IB8 * L0 * 1 SS (0) EOR (0) 0 CP6 (0) 0 IB7 * 0 * 1 0 0 0 0 0 IB6 ID6 0 * 0 0 0 0 0 0 IB5 ID5 0 * 0 0 NW5 (0) ID1 (1) CP5 (0) CP17 (0) Lower Code IB4 ID4 0 * 0 NL4 (1) NW4 (0) ID0 (1) CP4 (0) CP16 (0) IB3 ID3 0 * 0 NL3 (1) NW3 (0) AM (0) CP3 (0) CP15 (0) IB2 ID2 0 * 1 NL2 (1) NW2 (0) LG2 (0) CP2 (0) CP14 (0) IB1 ID21 0 * 1 NL1 (0) NW1 (0) LG1 (0) CP1 (0) CP13 (0) IB0 ID0 0 1 1 NL0 (1) NW0 (0) LG0 (0) CP0 (0) CP12 (0) Note
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh
787
NO1 (0) 0 0
NO0 (0) 0 0
SDT1 (0) 0 0
SDT0 (0) 0 TG0 (1)
EQ1 (0) 0 0
DIV0 (0) RM (0) CLW2 CLW1 CLW0 (0) (0) (0) 0 0
EQ0 (0)
DIV1 (0)
0 0 0
0 0 0
0
0
RTN3 (0) 0 0
RTN2 (0) 0 STG2 (0)
DM0 DM1 (0) (0) SHW1 SHW0 (0) (0)
RTN1 (0) RIM1 (0) STG1 (0)
RTN0 (0) RIM0 (0) STG0 (0)
0
0
1*
Power Control
10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh
0
VCOM VDV4 (0) G
2*
RAM Access
0 0 0 0 0 0 0 0 0 0 0 0
RAM Write Data (WD17-0 /RAM Read Data (RD17-0) *Bit assignment changes depending on the interface to be selected. 0 0 WM11 WM10 (0) (0) 0 0 WM9 (0) 0 WM8 (0) 0 WM7 (0) 0 WM6 (0) 0 0 0 0 0 WM5 WM4 WM3 WM2 WM1 WM0 (0) (0) (0) (0) (0) (0) WM17 WM16 WM15 WM14 WM13 WM12 (0) (0) (0) (0) (0) (0)
0 0 0 0 0 0 0 0 0 0 0 0
3*
Control
30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh * * *
Control (1) Control (2) Control (3) Control (4) Control (5) Control (6) Control (7) Control (8) Control (9) Control (10)
Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Vertical Scroll Control First Screen Driving Position Second Screen Driving Position Horizontal RAM Address Position Vertical RAM Address Position Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled Setting Disabled
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PKP12 (0) PKP32 (0) PKP52 0 0 (0) PRP12 0 0 (0) PKN12 0 0 (0) PKN32 0 0 (0) PKN52 0 0 (0) PRN12 0 0 (0) VRP14 VRP13 VRP12 (0) (0) (0) VRN14 VRN13 VRN12 (0) (0) (0) 0 0 0 0
PKP11 (0) PKP31 (0) PKP51 (0) PRP11 (0) PKN11 (0) PKN31 (0) PKN51 (0) PRN11 (0) VRP11 (0) VRN11 (0)
PKP10 (0) PKP30 (0) PKP50 (0) PRP10 (0) PKN10 (0) PKN30 (0) PKN50 (0) PRN10 (0) VRP10 (0) VRN10 (0)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PKP02 (0) PKP22 (0) PKP42 0 (0) PRP02 0 (0) PKN02 0 (0) PKN22 0 (0) PKN42 0 (0) PRN02 0 (0) VRP03 VRP02 (0) (0) VRN03 VRN02 (0) (0) 0 0
PKP01 (0) PKP21 (0) PKP41 (0) PRP01 (0) PKN01 (0) PKN21 (0) PKN41 (0) PRN01 (0) VRP01 (0) VRN01 (0)
PKP00 (0) PKP20 (0) PKP40 (0) PRP00 (0) PKN00 (0) PKN20 (0) PKN40 (0) PRN00 (0) VRP00 (0) VRN00 (0)
0 0 0 0 0 0 0 0
4*
Coordination Control
0 0 SE17 (1) SE27 (1) HEA7 (1) VEA7 (1) 0 SE16 (1) SE26 (1) HEA6 (0) VEA6 (1) 0 SE15 (1) SE25 (1) HEA5 (1) VEA5 (1) 0 SE14 (1) SE24 (1) HEA4 (0) VEA4 (0) 0 SE13 (1) SE23 (1) HEA3 (1) VEA3 (1) 0 SE12 (1) SE22 (1) HEA2 (1) VEA2 (1) 0 SE11 (1) SE21 (1) HEA1 (1) VEA1 (1) 0 SE10 (1) SE20 (1) HEA0 (1) VEA0 (1) VL7 (0) SS17 (0) SS27 (0) HSA7 (0) VSA7 (0) VL6 (0) SS16 (0) SS26 (0) HSA6 (0) VSA6 (0) VL5 (0) SS15 (0) SS25 (0) HSA5 (0) VSA5 (0) VL4 (0) SS14 (0) SS24 (0) HSA4 (0) VSA4 (0) VL3 (0) SS13 (0) SS23 (0) HSA3 (0) VSA3 (0) VL2 (0) SS12 (0) SS22 (0) HSA2 (0) VSA2 (0) VL1 (0) SS11 (0) SS21 (0) HSA1 (0) VSA1 (0) VL0 (0) SS10 (0) SS20 (0) HSA0 (0) VSA0 (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5* 6* 7*
Note 1) The numerals in parenthesis in the bit cells are initialized value. Note 2) Do not access to the"Setting Disabled" indexes.
Rev.0.22, May.23.2003, page 70 of 159
HD66787
Preliminary
Reset Function
The HD66787 makes internal initialization with RESET input. During RESET, the HD66787 is in a busy state, and no instruction from the MPU and access to GRAM are accepted. The time required for the RESET input is at least 1ms. In case of power-on reset, wait at least 10ms after the power is turned on until the R-C oscillation frequency becomes stabilized. While waiting, do not make an initial setting for the instruction set or an access to GRAM. Initial State of Instructions a. b. c. d. e. f. g. h. i. j. k. l. m. n. o. p. q. Start oscillation Driver output control (NL4-0 = "11101", SS = "0", SM = "0", EPL = "0", DPL = "0", HSPL = "0", VSPL = "0") Liquid crystal AC drive control (B/C = "0", EOR = "0", NW5-0 = "00000") Entry mode set (HWM = "0", I/D1-0 = "11": Increment by 1, AM = "0" : Horizontal direction, LG2-0 = "000" : Replace mode, BGR = "0", TRI = "0", DFM1-0 = "00") Compare register (CP17-0 : "00 0000 0000 0000 0000") Display control 1 (PT1-0 = "00", VLE2-1 = "00" : No vertical scroll, SPT = "0", DTE = "0", CL = "0" : 65,536-color mode, REV = "0", D1-0 = "00" : Display OFF) Display control 2 (BP3-0 = "1000", FP3-0 = "1000") Frame cycle control (NO1-0 = "00", SDT1-0 = "00", EQ1-0 = "00" : No equalization, DIV1-0 = "00": clock/1, RTN3-0 = "0000" : 16 clocks in 1H period) External display interface (RIM1-0 = "00" : 18-bit RGB interface, DM1-0 = "00" : internal clock operation, RM = "0" : System interface) LTPS interface control (TG0 = "1", STG2-0 = "000", SHW1-0 = "00", CLW2-0 = "000") Power control 1 (SAP2-0 = "000", BT2-0 = "000", AP2-0 = "000": liquid crystal power off, DK = "1" : DCDC1 off, SLP = "0", STB = "0" : Standby mode off) Power control 2 (DC12-0 = "000", DC02-00 = "000", VC2-0 = "000") Power control 3 (PON = "0", VRH3-0 = "00000") Power control 4 (VCOMG = "0", VDV4-0 = "00000", VCM4-0 = "00000") RAM address set (AD15-0 = "0000"H) RAM write data mask (WM17-0 = "18'h00000": No mask) control (PKP02-00 = "000", PKP12-10 = "000", PKP22-20 = "000", PKP32-30 = "000", PKP42-40 = "000", PKP52-50 = "000", PRP02-00 = "000", PRP12-10 = "000") (PKN02-00 = "000", PKN12-10 = "000", PKN22-20 = "000", PKN32-30 = "000", PKN42-40 = "000", PKN52-50 = "000", PRN02-00 = "000", PRN12-10 = "000") (VRP14-10 = "00000", VRP03-00 = "0000", VRN14-10 = "00000", VRN12-10 = "000") Vertical scroll (VL7-0 = "00000000") 1st split screen (SE17-10 = "11111111", SS17-10 = "00000000") 2nd split screen (SE27-20 = "11111111", SS27-20 = "00000000") Horizontal RAM address position (HEA7-0 = "10000011", HSA7-0 = "00000000") Vertical RAM address position (VEA7-0 = "10101111", VSA7-0 = "00000000")
r. s. t. u. v.
Rev.0.22, May.23.2003, page 71 of 159
HD66787 GRAM Data Initialization
Preliminary
The data in GRAM are not initialized by the RESET input. Initialize through software during the display OFF (D1-0 = "00"). Initial state of Output Pins a. b. Liquid crystal driver output pins (source outputs): Output GND level Oscillator output pin (OSC2): Outputs oscillation signal
Rev.0.22, May.23.2003, page 72 of 159
HD66787
Preliminary
Interface Specifications
The HD66787 incorporates a system interface to make settings for instructions, and an external display interface to display moving pictures. By selecting an optimum interface for display (moving or still picture, or both), data are transmitted efficiently. The external display interfaces are RGB-I/F and VSYNC-I/F. Through these interfaces, the data can be updated without flickering the moving picture on the display. In the RGB-I/F mode, the display operation is performed in synchronization with the signals (VSYNC, HSYNC, and DOTCLK). The display data are written according to the values of the data enable signal (ENABLE), data valid signal (VLD) and PD17-0 bits in synchronization with VSYNC, HSYNC, and DOTCLK signals. The display data are written to GRAM to reduce the data transmission to minimum, i.e. only when the displays are being updated. With the window address function, only the RAM area used for moving picture display is overwritten, and therefore the simultaneous display of moving picture area, which is overwritten, and the RAM data in the area other than the moving picture area, which is not overwritten, is possible. In the RGB and VSYNC interface modes, write data to GRAM in the high speed write mode (HWM = 1) while displaying moving pictures to make an access to GRAM in high speed with low power consumption. In the VSYNC interface mode, internal display operations are synchronized with the frame-synchronizing signal (VSYNC). By writing data in synchronization with the falling edge of VSYNC at a fixed speed to GRAM through a system interface, it enables moving pictures display with a system interface. In this case, there are some constraints in the RAM writing speed and method. The HD66787 handles the following 4 operational modes for the type of display. The setting can be made through an external display interface. A transition between the modes must follow the transition flow.
Rev.0.22, May.23.2003, page 73 of 159
HD66787 Operation modes and interfaces
Operation Mode Internal operating clock only (Displaying still pictures) RGB interface (1) (Displaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (Displaying moving pictures) RAM Access Setting (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0)
Preliminary
Display Operation Mode (DM1-0) Internal operating clock (DM1-0 = 00) RGB interface (DM1-0 = 01) RGB interface (DM1-0 = 01) VSYNC interface (DM1-0 = 10)
Note 1) the instruction register setting can be made only through a system interface. Note 2) The RGB-I/F and VSYNC-I/F are not compatible with each other. Note 3) Do not change the setting for RGB-I/F mode (RIM-0) while RGB I/F is in operation. Note 4) See the "External Display Interface" section for the transition flow of each operation mode. Note 5) In the RGB-I/F and VSYNC-I/F modes, write data in the high speed write mode (HWM = 1).
System interface
CSn* RS WR* (RD*) DB17-0 18/16/9/8 VLD ENABLE VSYNC HSYNC DOTCLK PD17-0 18/16/6
System
HD66787
RGB interface
Interfaces and HD66787
Rev.0.22, May.23.2003, page 74 of 159
HD66787
Preliminary
System Interface
The following shows the kinds of system interfaces and the IM pins setting for selecting an interface. The instruction setting and RAM access are made through a system interface. IM bits setting and the type of system interface
IM3 0 0 0 0 0 0 1 1 1 1 1 IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0 0 1 0 1 * * 0 1 0 1 * MPU-Interface Mode Setting disabled Setting disabled 80-system 16-bit interface 80-system 8-bit interface Serial peripheral interface (SPI) Setting disabled Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled DB17 to 0 DB17 to 9 DB17 to 10 and 8-to-1 DB17 to 10 SDI, SDO DB Pin
Rev.0.22, May.23.2003, page 75 of 159
HD66787 80-system 18-bit interface
Preliminary
80-system 18-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to IOVcc/GND/IOVcc/GND levels respectively.
MPU
CSn* A1 HWR* (RD*) D31-0 18
CS* RS WR* (RD*) DB17-0
HD66787
18-bit microcomputer and HD66787
Instruction
Input DB DB DB 17 16 15 DB DB 14 13 DB 12 DB DB 11 10 DB 9 DB 8 DB DB 7 6 DB 5 DB 4 DB 3 DB DB 2 1 DB 0
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB DB DB 12 10 9 DB 8 DB 7 DB DB 6 5 DB 4 DB 3 DB 2 DB 1 DB 0
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel 262,144 colors are available in 18-bit system interface
Data format for 18-bit interface
Rev.0.22, May.23.2003, page 76 of 159
HD66787 80-system 16-bit interface
Preliminary
The 80-system 16-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to GND/GND/IOVcc/GND levels respectively.
CSn* A1 H8/2245 HWR* (RD*) D15-0 16
CS* RS WR* (RD*)
HD66787
DB17-10, 8-1
16-bit microcomputer and HD66787
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
Input
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB 6
DB 5
DB 4
DB 3
DB 2
DB 1
GRAM R5 write data
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
66,536 colors are available in 16-bit system interface.
Data format for 16-bit interface
Rev.0.22, May.23.2003, page 77 of 159
HD66787 80-system 9-bit interface
Preliminary
The 80-system 9-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to IOVcc/GND/IOVcc/IOVcc levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits (the LSB is not used) and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 9 bits, and the upper bits are transmitted first. The unused pins DB8-0 pins must be fixed to either IOVcc or GND level. When writing into the index register, the upper byte (8 bits) must be written.
H8/2254
CSn* A1 HWR* (RD*) D15-0 9 9 GND
CS* RS WR* (RD*) DB17-9 DB8-0
HD66787
9-bit microcomputer and HD66787
Instructions
1st Transfer (Upper) Input DB DB 17 16 DB 15 DB 14 DB 13 DB DB 12 11 DB 10 DB 9 DB 17 2nd Transfer (Lower) DB DB 16 15 DB 14 DB 13 DB 12 DB DB 11 10 DB 9
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
1st Transmission (Upper) Input DB DB 17 16 DB 15 DB 14 DB 13 DB DB 12 11 DB 10 DB 9 DB 17 2nd Transmission (Lower) DB DB 16 15 DB 14 DB 13 DB 12 DB DB 11 10 DB 9
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel 262,144 colors are available in the 9 - bit system interface.
Data format for 9-bit interface
Rev.0.22, May.23.2003, page 78 of 159
HD66787 Data transmission synchronizing in 9-bit bus interface mode
Preliminary
The HD66787 supports a data transmission synchronizing function, which resets the upper/lower counter that counts the number of transmission of upper/lower 9-bit data in the 9-bit bus interface mode. When a discrepancy occurs in the upper/lower 9-bit data transmission due to effects from noise and so on, the "00" H instruction is written 4 times consecutively to forcibly reset the upper/lower counter so that data transmission restarts with an upper 9-bit data transmission. The excursion can be recovered by executing the synchronizing function periodically.
RS
RD
WR Upper Lower 00H (1) 00H (2) 00H (3) 00H (4) (9-bit transmission synchronization)
DB17-9
Upper
Lower
9-bit data transmission synchronization 80-system 8-bit interface The 80-system 8-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to GND/GND/IOVcc/IOVcc levels respectively. When transmitting a 16-bit instruction, it is divided into upper and lower 8 bits and the upper 8 bits are transmitted first. The RAM data is also divided into the upper and lower 8 bits, and the upper bits are transmitted first. The data to write to RAM are expanded into 18 bits internally. The unused pins DB9-0 must be fixed to either IOVcc or GND level. When writing into the index register, the upper byte (8 bits) must be written.
H8/2245
CSn* A1 HWR* (RD*) D15-0 8 10 GND
CS * RS WR* (RD*) DB17-10 DB9-0
HD66787 6
8-bit microcomputer and HD66787
Rev.0.22, May.23.2003, page 79 of 159
HD66787
Instruction
1st Transfer (Upper) Input DB DB 17 16 DB DB DB 15 14 13 DB DB 12 11 DB 10 DB 17 2nd Transfer (Lower) DB DB 16 15 DB DB DB 14 13 12 DB DB 11 10
Preliminary
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
Input DB DB 17 16 1st Transfer (Upper) DB 15 DB 14 DB DB 13 12 DB 11 DB 10 2nd Transfer (Lower) DB DB DB 17 16 15 DB DB 14 13 DB 12 DB DB 11 10
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
65,536 colors are available in 8 - bit system interface.
RAM data write : TRI =1, DFM1-0 = 10
1st Transmission INPUT DB DB DB DB DB DB DB 17 16 15 14 13 12 17 2nd Transmission DB 16 DB DB 15 14 DB DB 13 12 3rd Transmission DB DB DB 17 16 15 DB DB 14 13 DB 12
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
262,144 colors are available in 8 - bit system interface.
RAM data write : TRI =1, DFM1-0 = 11
1st Transmission INPUT DB DB DB DB DB DB DB 17 16 15 14 13 12 17 2nd Transmission DB 16 DB DB 15 14 DB DB 13 12 3rd Transmission DB DB DB 17 16 15 DB DB 14 13 DB 12
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
65,636 colors are available in 8 - bit system interface.
Data format for 8-bit interface
Rev.0.22, May.23.2003, page 80 of 159
HD66787 Data transmission synchronization in 8-bit bus interface mode
Preliminary
The HD66787 supports a data transmission synchronizing function, which resets the upper/lower counter that counts the number of transmission of upper/lower 8-bit data in the 8-bit bus interface mode. When a discrepancy occurs in the transmission of upper/lower 8-bit data due to effects from noise and so on, the "00" H instruction is written 4 times consecutively to forcibly reset the upper/lower counter so that data transmission restarts with the upper 8-bit transmission. The excursion can be recovered by executing the synchronizing function periodically.
RS
RD
WR
DB17-10
Upper/ Lower
00H (1)
00H (2)
00H (3)
00H (4)
Upper
Lower
e (8-bit transf r synchronization)
8-bit data transmission synchronization
Rev.0.22, May.23.2003, page 81 of 159
HD66787 Serial Peripheral interface (SPI)
Preliminary
The Serial Peripheral Interface (SPI) becomes operable by setting IM3/2/1 pins to GND/IOVcc/GND levels respectively. The SPI is available through the chip select line (CS*), serial transfer clock line (SCL), serial data input (SDI), and serial data output (SDO). In the SPI mode, the IM0/ID pin functions as ID pin. In the SPI mode, the unused DB15-2 pins must be fixed at either IOVcc or GND level. The HD66787 recognizes the start of data transfer at the falling edge of CS* input to initiate the transfer of start byte. It recognizes the end of data transfer at the rising edge of CS* input. The HD66787 is selected when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device identification code assigned to the HD66787 are compared and the both 6-bit data correspond. When selected, the HD66787starts taking in the subsequent data string. The setting for the least significant bit of the identification code is made with the ID pin. The five upper bits of the identification code must be 01110. Two different chip addresses must be assigned to the HD66787 because the seventh bit of the start byte is assigned to a register select bit (RS). When RS = 0, index register write or status read is executed. When RS = 1, instruction write or RAM read/write is executed. The eighth bit of the start byte is to specify read or write (R/W bit). The data are received when the R/W bit is 0, and are transmitted when the R/W bit is 1. In the SPI mode, the data are written to GRAM after two-byte data transmission. The data are expanded into 18 bits by adding one bit (the same data as the MSB of RB) next to the LSB of RB data. After receiving the start byte, the HD66787 starts to transmit or receive data by byte. The data transmission adopts a format by which the MSB is first transmitted. All HD66787 instructions consist of 16 bits and they are executed internally after two bytes are transmitted with the MSB first (DB15 to 0). The data to write to RAM are expanded into 18-bit data. After the start byte is received, the first byte is always fetched as the upper eight bits of the instruction and the second byte is fetched as the lower eight bits of the instruction. The 4-byte data that are read from RAM right after the start byte are made invalid. The HD66789 reads as valid data from the 5th-byte data. Start Byte Format
Transmitted bits Start byte format S Transmission start 1 2 3 4 5 6 7 RS 1 0 ID 8 R/W
Device ID code 0 1 1
Note 1) ID bit is selected with the IM0/ID pin.
RS and R/W Bit Function
RS 0 0 1 1 R/W 0 1 0 1 Function Set index register Read status Write instruction or RAM data Read instruction or RAM data
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HD66787
1st Transmission (Upper) Input D15 D14 D13 D12 D11 D10 D9 D8 D7
Preliminary
2nd Transmission (Lower) D6 D5 D4 D3 D2 D1 D0
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
1st Transmission (Upper) Input D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
2nd Transmission (Lower) D5 D4 D3 D2 D1 D0
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
66,536 colors are available in serial interface.
Data format for SPI
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HD66787
A)Basic data transmission through SPI
Data transmission start
Preliminary
Data transmission end
CS* (Input)
SCL (Input) SDI (Input)
1
2
3
4
5
6
7
8
9 10
11 12
13 14 15 16
17 18 19 20 21 22 23
24
MSB
"0" "1" "1" "1" "0" Device ID code
ID RS RS RW RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
LSB
D0
Start byte
Index register setting, instruction, RAM data write
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO (Output)
Status read, instruction read, RAM data read
B)Consecutive data transmission through SPI
CS* (Input)
1 234 5 67 8 9 10 1112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCL (Input)
SDI (Input)
Start byte Start
Instruction1: upper eight bits
Instruction1: lower eight bits
Instruction2: upper eight bits Instruction1: execution time End
Note: The first byte after the start byte is always the upper eight bits.
C) RAM data read transmission
CS* (Input) SCL (Input) SDI (Input) SDO (Output) Start Note: Five bytes of invalid dummy data are read after the start byte. The valid data are read from the 6th byte.
Start byte RS = 1, R/W = 1 Dummy Read 1 Dummy Read 2 Dummy Read 3 Dummy Read 4 Dummy Read 5
RAM read Upper 8 bits RAM read Lower 8 bits
End
D) Status read / instruction read
CS* (Input) SCL (Input) SDI (Input) SDO (Output) Start Note: One byte of invalid dummy data are read after the start byte. The valid data are read from the second byte.
Start byte RS = 1, R/W = 1
Dummy read 1
Status read: upper eight bits
Status read: lower eight bits
End
Data transmission through SPI
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HD66787
Preliminary
VSYNC Interface
The HD66787 incorporates a VSYNC-I/F, which enables moving picture display with only a system interface and the frame-synchronizing signal (VSYNC). This interface enables moving picture display with minimum modification to a conventional system.
VSYNC HD66787 LCDC/ MPU CS* RS WR* 16 DB17-10, 8-1
VYSNC interface The VSYNC-I/F becomes operable by setting DM1-0 = 10 and RM = 0. In the VSYNC I/F mode, the internal display operations are synchronized with VSYNC. By writing data to RAM through a system interface in a speed that is higher for more than a fixed speed than the internal display operation speed, it enables moving picture display through a system interface, while preventing flickers while the screens are being updated. Display operations are executed by the internal clock generated by the internal oscillator and VSYNC input. All display data are stored in RAM. This enables moving picture display only by transmitting data that are written over, thereby minimizing the number of data transmission while displaying moving picture. The high-speed write mode (HWM = 1) enables RAM access in high speed with low power consumption.
VSYNC
RAM write via system interface
Updating screen
Updating screen
Display operation in synchronization with the internal clock
Note: Data must be written in the high-speed write mode (HWM = 1) in VSYNC-I/F mode.
Moving picture data transmission through VSYNC interface
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HD66787
Preliminary
The VSYNC-I/F has limits on the minimum speed and the frequency of the internal clock for the RAM write through system interface. It requires a RAM write speed more than the result that is calculated from the following formula.
* * Internal clock frequency (fosc) [Hz] = Frame frequency x (Display line (NL) + Front porch (FP) + Back porch (BP)) x 16 clocks x Fluctuation Minimum speed for RAM write (min.)[Hz] > 176 x Display line (NL) / {((Back porch (BP) + Display raster-row (NL) - Margin) x 16 clock) / fosc}
Note 1) When RAM write does not start right after the falling edge of VSYNC, the time between the falling edge of VSYNC and the start of RAM write must also be taken into account.
An example of RAM write speed and the frequency of the internal clock in the VSYNC interface mode is as follows. [Example] Display size Display line Back/front porch Frame frequency 176 RGB x 240 lines 240 lines (NL = 11110) 14/2 lines (BP = 1110/FP = 0010) 60 Hz
Internal clock frequency (fosc) [Hz] = 60 Hz x (240 + 2 + 14) x 16 Clock x 1.1 / 0.9 = 300 kHz When calculating the internal clock frequency, possible causes of fluctuations must also be taken into consideration. The allowance for this fluctuation is 10 % from the center value, and the range of the frequency must be within VSYNC period. As the causes of fluctuations, the above example takes the variation in the LSI fabrication and the room temperature into account. Other possible causes of fluctuations, such as variation in the external resistors or the voltage change are not considered in the above example. It is necessary to make a setting with enough margins to include the allowances for these factors. Minimum speed for RAM writing [Hz] > 176 x 240 / {((14 + 240 - 2) raster-rows x 16 clock) / 300 kHz} = 3.14 MHz In this case, RAM write is performed in synchronization with the falling edge of VSYNC. When the data for one frame are written to RAM completely, there must be more than 2 raster-rows of margin before the raster-row starts to drive for the next frame. By writing data to RAM on the falling edge of VSYNC at the speed of 3.14 MHz or more, the data for the whole screen on RAM are overwritten before the display operation starts. Accordingly, the flicker due to updating moving picture data can be avoided while displaying a moving picture.
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HD66787
VSYNC RAM write at 10MHz 44240 times R-C oscillation 10%
Preliminary
RAM write Back porch (14 raster-rows)
Raster-row 240
The number of driven raster-rows
Display operation RAM write at 3.15 MHz
Display (240 raster-rows)
Display operation
Display operation
Front porch (2 raster-rows) Blanking period
0
Back-porch 14H
[ms] 4.22 13.41 13.55 16.74 60Hz
VSYNC
Operation through VSYNC interface Notes to the VSYNC interface 1. The aforementioned example of calculation is just a result of calculation. In the actual settings, causes for the fluctuations such as internal clocks should be taken into consideration. It is necessary to make a setting for RAM write speed with enough margins. The aforementioned example of calculation is the value in case of writing over the entire screen. Limiting the area for the moving picture display will create more margins for the RAM write speed.
R-C oscillation 10% Display operation
2.
VSYNC Back porch (14 raster-rows) (20 raster-rows)
Raster-row 240 220
The number of driven raster-rows
RAM write at 3.15 MHz Display operation
Moving picture area (200 raster-rows)
20 0
Back-porch 14H
(20 raster-rows) Front porch (2 raster-rows) VSYNC
4.22
11.17 13.55
[ms] 13.52 16.74 60Hz
Limiting moving picture display area 3. 4. 5. 6. 7. A front porch period continues after the completion of 1 frame display and until the next input of VSYNC. The transition between the internal clock operation mode (DM1-0 = 00) and the VSYNC interface mode becomes effective after displaying one frame made during instruction setting. In the VSYNC interface mode, the partial display, vertical scroll, and interlaced drive functions are not available. In the VSYNC interface mode, set AM to 0 to transmit display data in the aforementioned method. In the VSYNC interface mode, write display data to RAM in the high speed write mode (HWM = 1)
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HD66787
Internal Clock Operation to VSYNC Interface
Internal clock operation
Preliminary
VSYNC Interface to Internal Clock Operation
VSYNC interface operation
Display operation in synchronization with VSYNC The values set in DM1-0 and RM become valid after completion of 1-frame display.
HWM = 1, AM = 0 Address Setting VSYNC interface mode setting (DM1-0 = 0, RM = 0) Index register set (R22h) Wait more than 1 frame VSYNC interface Write data to RAM VSYNC interface operation
Internal clock mode setting (DM1-0 =00, RM = 0)
Displa y operation in synchronization with VSYNC Display operation in synchronization with the internal clock The values set in DM1-0 and RM become valid after completion of 1-frame display.
Internal clock mode setting (DM1-0 = 0, RM = 0)
Wait more than 1 frame Internal clock operation
Display operation in synchronization with the internal clock
Note: When switching into the internal clock mode,the VSYNC signal must be kept continuously supplied for more than 1 frame after it is switched into the internal clock mode.
Wait more than 1 frame Internal clock operation
Note: When t he interface mode is switched, VSYNC should be input before setting of DM1-0 and RM.
Transition flow between VSYNC and internal clock operation modes
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HD66787
Preliminary
External Display Interface
The following interfaces are available as the external display interface (RGB interface). The interface is selected by setting RIM1-0 bits. RAM is accessible through the RGB interface. RIM bits setting and RGB interface
RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface PD Pin
18-bit RGB interface 16-bit RGB interface 6-bit RGB interface Setting disabled
PD17-0 PD17-13, 11-1 PD17-12
Note 1) The use of multiple interfaces simultaneously is not possible.
RGB interface Through the RGB-I/F, the display operation is performed in synchronization with VSYNC, HSYNC, and DOTCLK. The RGB interface enables data transmission with low power consumption by overwriting the area that needs update in high-speed write mode in combination with the window address function. The front and back porches must be set before and after the display period.
VSYNC Back porch period (BP3-0)
Display area for RAM data
Display area for moving pictures
Display period (NL4-0)
Front porch period (FP3-0)
HSYNC DOTCLK ENABLE VLD PD17-0 VSYNC: Frame synchronization signal HSYNC: Raster-row synchronization signal DOTCLK: Dot clock ENABLE: Data enable signal VLD: Data valid signal PD17-0: Display data for RGB (6:6:6)
Note 1) The front porch period continues until the next input of VSYNC signal. Note 2) The DOTCLK signal must be supplied consecutively.
Back porch period (BPP):14H>=BP3-0>=2H Front porch period (FPP):14H>=FP3-0>=2H FPP + BPP =<16H Display operation period: NL4-0 =< 240H The number of raster-rows of 1 frame: FPP + DP + BPP
Note 3) In RGB interface mode, VSYNC, HSYNC, and DOTCLK more than to achieve the LCD resolution must be supplied.
RGB interface
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HD66787 VLD and ENABLE signals
Preliminary
The relationship with the VLD and ENABLE signals is as follows. With the ENABLE signal, the addresses are not updated during data write, while with the VLD signal, the addresses are updated during data write when the ENABLE is "Low". The polarity of the ENABLE signal is inverted by the setting of EPL bit.
EPL 0 0 0 1 1 1 ENABLE 0 0 1 0 1 1 VLD 0 1 * * 0 1 RAM Write Valid Invalid Invalid Invalid Valid Invalid RAM Address Updated Updated Unchanged Unchanged Updated Updated
RGB interface timing The timing chart of 16/18-bit RGB interfaces is as follows.
1 frame
Back porch period Front porch period
VSYNC HSYNC DOTCLK C ENABLE VLD PD17-0
>=1H VSYNC 1H
HLW >= 1CLK
HSYNC 1 clock DOTCLK
DTST >=HLW
ENABLE VL D
PD17-0 Valid data VLW: the period in which VSYNC is low level HLW: the period in which HSYNC is low level DTST: the set up time for data transmission Note: Data to be displayed must be written in the high-speed write mode (HWM = 1) in RGB I/F mode.
16-/18-bit RGB Interface Timing
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HD66787 The timing chart of 6-bit RGB interface is as follows.
1 frame
Back porch period Front porch period
Preliminary
VSYNC HSYNC DOTCLK ENABLE VLD PD17-0
>= 1H VSYNC 1H HLW>=3CLK HSYNC 1 clock DOTCLK DTST >= HLW ENABLE VLD
RGB RGB RGB RGB RGB
PD17-0 Valid data VLW: the period in which VSYNC is low level HLW: the period in which HSYNC is low level DTST: the set up time for data transmission Note 1) In 6-bit interface.mode, one pixel, which consists of R,G, and B, must be transmitted in synchronization with 3 DOTCLKs. Note 2) VSYNC, HSYNC, EVABLE, DOTCLK, VLD, and PD17-2 should be all transmitted by three clocks. Note 3) Data to be displayed must be written in the high-speed write mode (HWM =1) in RGB I/F mode.
6-bit RGB Interface Timing
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HD66787 Moving picture display
Preliminary
The HD66787 incorporates the RGB interface to display moving pictures and RAM to store display data, which provides the following merits in displaying moving pictures. * * * * * The window address function enables the transfer of only the data for the moving picture area. The high-speed write modes enables high-speed access to RAM with low power consumption Only transmitting the data that are written over the moving picture area. By reducing the amount of data transmission, the power consumption of the whole system is reduced. In combination with a system interface the still picture area, such as an icon, can be updated while displaying moving pictures.
RAM access through system interface in RGB-I/F mode RAM is accessible through a system interface in the RGB-I/F mode. In the RGB interface mode, data are being written to RAM in synchronization with the DOTCLK input while the ENABLE is "Low". When writing data to RAM through the system interface, it is necessary to set ENABLE to "High" to stop data write through the RGB-I/F. Setting RM = 0 allows RAM access through the system interface. When reverting to the RGB interface mode, wait a write/read bus cycle. Then, set RM = 1 and the index to R22h to start RAM access though the RGB-I/F. When the RAM writes through the RGB and system interface conflicts, it is not guaranteed that the data are properly written to RAM. The following is an example of moving picture display through the RGB-I/F and updating still picture area through the system interface.
Updating screen VSYNC ENABLE Updating screen
DOTCLK PD17-0 Index set System interface
Index R22 RM=0 Setting of address Index R22 Updating of area other than moving picture area
*Note 2
Setting of address RM=1 Index R22
Updating moving picture area
Updating of still picture area
* Note 1
Updating moving picture area
Note 1) In the RGB interface mode, the address is set at every falling edge of VSYNC. Note 2) Set the address and the index (R22h) before RAM access starts through the RGB interface mode. Note 3) In the RGB interface mode write data in the high-speed write mode (HWM = 1).
2001/01/01 00:00 Still picture area
Moving picture area
Updating Still Picture Area during Displaying Moving Picture
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HD66787 6-bit RGB interface
Preliminary
The 6-bit RGB interface is selected by setting RIM1-0 bits to 10. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through 6-bit RGB data bus (PD17-12) according to data valid signal (VLD), and the data enable signal (ENABLE). Unused pins (PD11 to 0) must be fixed to either IOVcc or GND level. The instructions are set only through a system interface.
VSYNC HSYNC DOTCLK LCDC VLD ENABLE PD17-12 6 12 GND PD11-0 HD66787
6-bit RGB interface
RAM data write
1st Transmission INPUT PD 17 PD 16 PD 15 PD 14 PD 13 PD PD 12 17 2nd Transmission PD PD 16 15 PD 14 PD 13 3rd Transmission PD PD PD PD PD PD PD 12 17 16 15 14 13 12
Write Data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One Pixel
262,144 colors are available in 6-bit system interface.
Data format for 6-bit interface Data transmission synchronization in 6-bit RGB interface mode The HD66787 incorporates a transmission counter to count the first, second, third data transmissions in the 6-bit RBG interface mode. The transmission counter is reset to the first transmission on the falling edge of VSYNC. When a discrepancy occurs in the transmission of first, second and third data, the counter is reset to the first data transmission at the start of each frame (on the falling edge of VSYNC) and the data transmission restarts in the correct order from the next frame. In case of displaying moving pictures, which requires consecutive data transfer, this function minimizes the effect from the discrepancy in the data transmission and makes it easy to return to the normal display. The internal display operation is executed by pixel. Note that each DOTCLK input must correspond to a pixel. Otherwise data transmission discrepancies will occur and affect the displays of the current and ensuing frames.
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HD66787
Preliminary
VSYNC
ENABLE DOTCLK
PD17-0
2nd Transmission
Transfer synchronization
2nd 3rd 1st 2nd 3rd 1st Trans- Trans- Trans- Trans- Trans- Transmission mission mission mission mission mission
6-bit data transmission synchronization 16-bit RGB interface The 16-bit RGB interface is selected by setting RIM1-0 bits to 01. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through 16-bit RGB data bus (PD17-13, 11-1) according to the data valid signal (VLD), and the data enable signal (ENABLE). The instructions are set only through system interface.
VSYNC HSYNC DOTCLK C LCDC HD66787 VLD ENABLE PD17-13,11- 1 16 2 GND PD12,0
16-bit RGB interface
RAM data Write
Input PD PD PD PD PD 17 16 15 14 13 PD PD PD PD PD 11 10 9 8 7 PD PD PD PD PD PD 6 5 4 3 2 1
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Data format for 16-bit interface
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HD66787 18-bit RGB interface
Preliminary
The 18-bit RGB interface is selected by setting RIM1-0 bits to 00. The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Display data are transmitted to RAM in synchronization with the display operation through 18-bit RGB data bus (PD17-0) according to the data valid signal (VLD), and the data enable signal (ENABLE). The instructions are set only through a system interface.
VSYNC HSYNC DOTCLK LCDC VLD ENABLE 18 PD17-0 HD66787
18-bit RGB interface
RAM data Write
Input PD PD PD PD PD PD 17 16 15 14 13 12 PD PD PD PD PD 11 10 9 8 7 PD PD PD PD PD PD 6 5 4 3 2 1 PD 0
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
262,144 colors available in 18-bit RGB interface.
Data format for 18-bit interface
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HD66787 Notes to the external display interface 1.
Preliminary
While an external display interface is selected, the following functions are not available.
External Display Interface Not available Not available Not available Internal Display Operation Available Available Available
Function Partial display Scroll function Graphics operation function
2. 3. 4. 5. 6. 7. 8. 9.
The VSYNC, HSYNC, and DOTCLK signals must be supplied consecutively during display operation through the RGB-I/F. When setting NO1-0, SDT1-0, and EQ1-0 bits in the RGB-I/F mode, the reference clock is the DOTCLK, not the internal operation clock. In the 6-bit RGB-I/F mode, RGB (pixels) data are transmitted by three clocks. The data transmission, therefore, should be made by RGB. In the 6-bit RGB-I/F mode, the interface signals, VSYNC, HSYNC, DOTCL, ENABLE, VLD, and PD17-0, should be set in RGB (pixels) in convenience for transmitting RGB pixels. The transitions between the internal operation mode and external display interface should be made according to the mode switching sequence below. In the RGB-I/F mode, the front porch period continues after displaying one frame data until the next VSYNC signal input. In the RGB-I/F mode, the data must be written in the high-speed write mode (HWM = 1). In the RGB-I/F mode, the address is set every frame on the falling edge of VSYNC.
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HD66787
Internal Clock Operation to RGB I/F (1)
Internal clock operation
Preliminary
RGB I/F (1) to Internal Clock Operation
RGB I/F operation
Display operation in synchronization with the RGB signals ( VSYNC , HSYNC, DOTCLK) The value set in DM1-0 and RM bits become valid after the completion of 1-frame display.
HWM = 1, AM = 0 Address Setting RGB I/F Setting (DM1-0=01, RM=1)
Index resister setting (R22h)
Display operation in synchronization with the internal clock The value set in DM1-0 and RM become valid after the completion of 1-frame display.
Internal clock mode setting (DM1-0 = 00, RM=0)
Wait more than 1 frame Internal clock operation
Display operation in synchronization with the internal clock
Wait more than 1 frame RGB I/F Writing RAM Data
Note: When switching into the internal clock mode from RGB I/F, keep RGB I/F signals (VSYNC, HSYNC, DOTCLK, ENABLE) input for more than 1 frame after the mode has been switched.
Display operation in synchronization with the RGB signal
RGB interface operation
Note: When switching into the RGB interface mode, the RGB interface signals, VSYNC, HSYNC, DOTCLK, and ENABLE, must be input before the setting of DM1-0 and RM bits.
Transition between the Internal Clock Operation Mode and RGB Interface Mode
From RGB I/F (1) to RGB I/F (2)
RGB I/F Operation System I/F Writing RAM Data
From RGB I/F (2) to RGB I/F (1)
RGB I/F mode setting (DM1-0=01, RM=0) HWM=1/0 Address Setting Index resister setting (R22h)
HWM=1, AM=0 Address Setting RGB I/F mode (DM1-0=01, RM=1) Index resister setting (R22h)
System I/F Writing RAM Data
RGB I/F Operation
RAM data write sequence through system interface in RGB-I/F mode
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HD66787
Preliminary
Timing Interfacing with Liquid Crystal Panel Signals
The relationship between RGB I/F signals and the liquid crystal panel signals in the RGB I/F mode is as follows (TG0 = "0").
Back porch period (BP)
1 frame
Front porch period (BP)
Back porch period (BP)
>=1H VSYNC 1H HSYNC DOTCLK ENABLE VLD PD17-0 12345
236 237 238 239 240
1
Note 1) 5DOTCLK FLM CLW2-0 CL1 SFTCLK DISPTMG NO1-0 G1 G2 SHW1-0 STG2-0 1H
Note 1) 5DOTCLK
G240 SDT1-0 12345
S1-528
236 237 238 239 240
EQ1-0 EQ M (VCOM) Note 1) 15 clocks in case of 6-bit RGB I/F mode. Note 2) FLM, CL1, SFTCLK, DISPTMG, and M can be output after level-shifted. EQ is an internal signal.
Relationship between RGB I/F signal and the liquid crystal panel signal (TG0 = "0")
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HD66787
Preliminary
The timing interfacing with the liquid crystal panel signals in the internal clock operation mode is as follows (TG0 = "0").
1-frame
Front porch period (FP) +Back porch period(BP) =8H
FLM CLW2-0 CL1 SFTCLK DISPTMG
1H
SHW1-0 STG2-0
NO1-0 G1 G2
G240 SDT1-0 12345
S1-528
236 237 238 239 240
1
EQ1-0 EQ M (VCOM)
Note 1) 15 clocks in case of 6-bit RGB I/F mode. Note 2) FLM, CL1, SFTCLK, DISPTMG, and M can be output after level-shifted. EQ is an internal signal.
Interfacing with the liquid crystal panel signals in the internal clock operation mode (TG0 = "0")
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HD66787
Preliminary
The timing interfacing with the liquid crystal panel signals in RGB interface mode is as follows (TG0 = "1").
1 Frame
Back Porch (BP) Front Porch (FP) Back Porch (BP)
1H or more
VSYNC
1H
HSYNC DOTCLK ENABLE VLD PD17-0
5 DOTCLKs Note 1)
1 2 3 4 5 236 237 238 239 240 1
1H
5 DOTCLKs Note 1)
FLM(TG0=1) FLM(TG0=0)
CLW 2-0 STG2-0
CL1(TG0=1) CL1(TG0=0) SFTCLK
(TG0=1) STG2-0
SFTCLK
(TG0=0)
DISPTMG
NO1-0
(G1) (G2) (G240)
SDT1-0
S1-528
1
2
3
4
5
236 237 238 239 240
EQ1-0
EQ M(VCOM)
Note 1) 15 DOTCLKs in 6-bit RGB I/F mode. Note 2) FLM,CL1, SFTCLK, DISPTMG and M are output after level-shifted. EQ is an internal signal.
Interfacing with the liquid crystal panel signals in RGB interface mode (TG0 = "1")
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HD66787
Preliminary
The timing interfacing with the liquid crystal panel signals in the internal clock operation mode is as follows (TG0 = "1").
1 Frame
Front porch (FP) + Back porch (BP) = 8H
1H
FLM (TG0 = 1) FLM CL1 CL1
(TG0 = 0) STG2-0
(TG0 = 1) CLW2-0 (TG0 = 0) STG2-0
SFTCLK
(TG0 = 1) SHW1-0 STG2-0
SFTCLK
(TG0 = 0) (TG0 = 0)
DISPTMG
NO1-0
(G1) (G2) (G240)
SDT1-0
S1-528
1
2
3
4
5
236 237 238 239 240 EQ1-0
1
EQ M(VCOM)
Note 1) 15 clocks in case of 6-bit RGB I/F mode. Note 2) FLM, CL1, SFTCLK, DISPTMG, and M can be output after level-shifted. EQ is an internal signal.
Interfacing with the liquid crystal panel signals in the internal clock operation mode (TG0 = "1")
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HD66787 Register settings CL1 signal: "Low" width
CLW 2 CLW 1 CLW 0 CL1 signal : pulse width during "Low"
internal operation (synchronized with the internal operating clock) RGB interface operation
Preliminary
(synchronized with DOTCLK)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks 8 clocks
8 clocks 16 clocks 24 clocks 32 clocks 40 clocks 48 clocks 56 clocks 64 clocks
Note 1) The number of clocks is counted from the falling edge of CL1 signal.
EQ signal: "High" width
EQ 1 EQ 0 EQ signal : pulse width during "High"
internal operation (synchronized with the internal operating clock) RGB interface operation (synchronized with DOTCLK)
0 0 1 1
0 1 0 1
No equalize 1 clock 2 clocks 3 clocks
No equalize 8 clocks 16 clocks 24 clocks
Source output delay
STD 1 STD 0 Source output delay
internal operation (synchronized with the internal operating clock) RGB interface operation (synchronized with DOTCLK)
0 0 1 1
0 1 0 1
1 clock 2 clocks 3 clocks 4 clocks
8 clocks 16 clocks 24 clocks 32 clocks
Note 1) The amount of source output delay is measured from the falling edge of CL1 signal.
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HD66787 Gate output non-overlap
STD 1 STD 0 Gate output non-overlap
internal operation (synchronized with the internal operating clock) RGB interface operation (synchronized with DOTCLK)
Preliminary
0 0 1 1
0 1 0 1
0 clock 4 clocks 6 clocks 8 clocks
0 clocks 32 clocks 48 clocks 64 clocks
Note 1) The amount of gate output non-overlap is measured from the falling edge of CL1 signal.
SFTCLK signal: pulse output position
STG 2 STG 1 STG 0 SFTCLK signal : pulse output position
internal operation (synchronized with the internal operating clock) RGB interface operation (synchronized with DOTCLK)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 clock 1 clock 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks
0 clock 8 clocks 16 clocks 24 clocks 32 clocks 40 clocks 48 clocks 56 clocks
Note 1) The number of clocks is counted from the falling edge of the CLT signal.
SFTCLK signal: purse width during "High"
SHW 1 SHW 0 SFTCLK signal : purse width during "High"
internal operation (synchronized with the internal operating clock) RGB interface operation (synchronized with DOTCLK)
0 0 1 1
0 1 0 1
1 clock 2 clocks 3 clocks 4 clocks
8 clocks 16 clocks 24 clocks 32 clocks
Rev.0.22, May.23.2003, page 103 of 159
HD66787
Preliminary
Low-temperature poli-Si TFT Panel Control
HD66787 outputs timing signals (FLM, CL1, SFTCLK) for controlling low-temperature poli-Si TFT (LTPS-TFT) panels with incorporated gates. By level-shifting the voltage of FLM, CL1, SFTCLK, and DISPTMG, the LTPS-TFT panel with incorporated gates becomes easily controllable. Source drivers (HD66787) * Output control timing signals (internal signal) FLM (Frame heading pulse) CL1 (Line cycle signal): "Low" width variable with CLW2-0 bits SFTCLK (Line cycle signal): output timing variable with STG2-0, SHW1-0 bits * * Level-shift output ports for LTPS VGH ~ VGL amplitude SOUT 11, SOUT 12, SOUT 13, SOUT 14, SOUT 21, SOUT 22, SOUT 23, SOUT 24
176 pixels x 3
VGH, VGL
G1 G2
Low-temperature poli-Si (LTPS) TFT 240
G239 G240
S1 S2
with incorporated gates
Shift Register
SOUT11 SOUT12 SOUT13 SOUT14
S527 S528
Driver circuits for incorporated gates
4
Vcom
SOUT21 SOUT22 SOUT23 SOUT24
Power supply Circuit Vcom
Level shift
HD66787
Level t Shif DCDC
18
4
3
18
4
Vcc GND Vci1 Vci
RESET
DB17-0
IM2,IM1, VLD PD17-0 IMO/ID VSYNC HSYNC DOTCLK ENABLE
CS*, WR* RD*, RS
System configuration
Rev.0.22, May.23.2003, page 104 of 159
HD66787 Output timing (HD66787)
Preliminary
HD66787 outputs timing signals (FLM, CL1, SFTCLK) for controlling low-temperature poli-Si TFT (LTPS-TFT) panels with incorporated gates. The output timing of CL1 can be adjusted by instructions for controlling LTPS-TFT interface. Set an optimum timing for the configuration of gate circuits incorporated in the LTPS-TFT panel in use.
FLM CL1 SFTCLK Source Output Example 1) Gate selection signal G1 G2 G3 Example 2) Non-overlap gate selection signal G1 G2 G3 1st Line 2nd Line 3rd Line 4th Line 5th Line
Example of connecting timing signals for LTPS
HD66787
CL1
LS
Incorporated gate circuit
LTPS-TFT
FLM
LS
LS : Voltage level-shift circuit
LTPS-TFT control
Note 1) Some gate circuit configuration incorporated in the LTPS-TFT may not allow the use of certain functions with HD66787.
Rev.0.22, May.23.2003, page 105 of 159
HD66787
Preliminary
High-Speed Burst RAM Write Function
The HD66787 incorporates high-speed burst RAM-write function, which writes data to RAM in one-fourth the access time required for a standard RAM-write operation. This function is especially useful for applications which require the high-speed rewrite of the display data such as display of colored moving picture and so on. In the high-speed RAM write mode (HWM), data to write to RAM is temporarily stored to the internal register of HD66787. The data storage in the register is executed by word. When the data storage operation is executed 4 times, all data stored in the register are written to RAM at once. While the data is being written from the register to RAM, another set of data is being written to the register. This function enables high-speed and consecutive RAM write, which are required in displaying moving pictures and so on.
Microcomputer
18
Address counter (AC) 16
Register 1
Register 2
Register 3 72
Register 4
"0000H"
"0001H"
"0002H"
"0003H" GRAM
Operational flow of High-Speed Burst RAM Write
CS* (input)
1 2 3 4 1 2 3 4 1 2 3 4
E (input) DB15-0 (input/output)
RAM Index RAM data data 1 (R22) 1 RAM data 2 RAM data 3 RAM data 4 RAM data 5 RAM data 6 RAM data 7 RAM data 8 RAM data 9 RAM data 10 RAM data 11 RAM data 12
Index (R22)
RAM write execution time RAM write data (72 bits)
RAM write execution time
RAM write execution time
RAM data 1 to 4
RAM data 5 to 8
RAM data 9 to 12
RAM address (AC15 to 0)
"0000"H
"0004"H
"0008"H
"000A"H
The lower two bits of the address must be set as follows in the high-speed write mode. When ID0 = 0, set the lower two bits of the address to 11. When ID1 = 1, set the lower two bits of the address to 00.
Note : When terminating the high-speed RAM write, wait for the time required for the RAM write execution (bus cycle line (tCYC) in the normal write mode) before executing the next instruction.
High-Speed Consecutive Write to RAM
Rev.0.22, May.23.2003, page 106 of 159
HD66787
Preliminary
CS* (input)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
E (input) DB15-0 (input/output)
Index (R22)
RAM data 1 Upper RAM data 1 lower RAM data 2 Upper RAM data 2 lower RAM data 3 Upper RAM data 3 lower RAM data 4 Upper RAM data 4 lower RAM data 1 Upper RAM data 1 lower RAM data 2 Upper RAM data 2 lower RAM data 3 Upper RAM data 3 lower RAM data 4 Upper RAM data 4 lower
RAM write execution time RAM write data (64 its) RAM data 1 to 4
RAM write execution time *Note RAM data 5 to 8
RAM address (AC15 to 0)
"0000"H
"0004"H
"The lower two bits of the address must be set as follows in high-speed write mode. When ID0 = 0, set the lower two bits of the address to 11. When ID1 = 1, set the lower two bits of the address to 00. Note : In the high-speed mode (HWM), data are written to the RAM every 4 words. This means in the 8-bit interface mode, data are written to the RAM for every eight write operation.
Operation of High-Speed Consecutive Writing to RAM (8-Bit Interface) Notes to the high-speed RAM write mode 1. 2. The logical/compare operations are not available. The RAM write operation is executed every four words. Set the lower 2 bits of the addresses as follows when setting addresses. *When ID0=0, the lower two bits in the address must be set to 11 before RAM write. *When ID0=1, the lower two bits in the address must be set to 00 before RAM write. 3. 4. The RAM write operation is executed every four words. If RAM write operation is terminated before all four-word data is written to RAM, the last data will not be written to RAM. When the index register is set to R22H (RAM data write), the first RAM write operation is always executed. In this case, RAM data read is not operable simultaneously. During RAM read, set the HWM to 0. The high-speed RAM write mode is not compatible with the normal RAM write mode. When the mode must be switched to the other, make a new address set before starting RAM write. When writing data in high speed RAM write mode within the range specified with the window address, some window-address range may require dummy write operation. See "High-Speed RAM Write with Window Address Function".
5. 6.
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HD66787 Comparison of Normal and High-Speed RAM Write Operations
Normal RAM Write (HWM=0) Logical operation function Compare operation function BGR function Write mask function RAM address set RAM read RAM write Window address External display interface AM Setting Available Available Available Available Specified by one word Read by one word Write by one word Set by one word Available AM = 1/0
Preliminary
High-Speed RAM Write (HWM=1) Not available Not available Available Available ID0 bit=0: Set the lower two bits to 11 ID0 bit=1: Set the lower two bits to 00 Not available Dummy write operations may be required depending on the specified window-address range Horizontal range(HSA/HSE): more than four words Number of horizontal writing : 4N (N>=2) Available AM = 0
High-Speed RAM Write with Window Address Function To rewrite the data in an arbitrary rectangular area of RAM consecutively in high speed, the number of RAM access should be made 4 multiple times. Accordingly some window-address range may require dummy write operation to make the RAM access 4 multiple times. The number of dummy write is set when setting the window address as follows. The horizontal window-address range specifying bits (HSA1-0, HEA1-0) specify the number of dummy write operations executed at the start and end of the data to write to RAM. The total RAM access must be 4 multiple times per line. Number of Dummy Write Operations in High-Speed RAM Write (HSA Bits)
HSA1 0 0 1 1 HSA0 0 1 0 1 Number of Dummy Write Operations inserted 0 1 2 3
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HD66787 Number of Dummy Write Operations in High-Speed RAM Write (HEA Bits)
HEA1 0 0 1 1 HEA0 0 1 0 1 Number of Dummy Write Operations Inserted 3 2 1 0
Preliminary
The number of RAM access when writing data in the horizontal direction must be made 4 x N times by including the dummy writes. Horizontal RAM write = start dummy write + write data + end dummy write = 4 x N (times) An example of RAM write in high speed RAM write mode with the window address is as follows. The RAM data in the specified window-address range is written over consecutively in high speed by inserting two dummy writes at the start of the line and three dummy writes at the end of the line. The number of dummy writes is specified with the window-address range specifying bits. In this case, set HSA1-0 to 10, HEA1-0 to 00.
Writing data in the horizontal direction AM = 0, ID0 = 1 Window address range setting HSA = h12, HEA = h30 VSA = h08, VEA = hA0 High-speed RAM write mode setting HWM = 1
h0000 h0812
GRAM address map
Specified window address range (rewrite area)
Address set AD = h0810 *Note
hA030
hEFAF
Dummy RAM write X 2
Window address range setting HAS = h12, HEA = h30 VSA = h08, VEA = hA0 X 153
RAM write X 31
Dummy RAM write X 3
Note: In the high-speed RAM write mode, the address set must be either 00 or 11 in ID0 bit setting. Only the RAM address range specified by window addresses will be overwritten.
High-Speed RAM Write with Window Address Function
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HD66787
Preliminary
Window Address Function
The window address function enables consecutive data write within the rectangular window-address area on the on-chip GRAM, which is specified with horizontal address registers (start: HSA7-0, end: HEA 7-0) and vertical address registers (start: VSA7-0, end: VEA7-0). The address transition direction is determined with AM bits (either increment or decrement). Accordingly, the data, including picture data, are written consecutively without taking the data wrap position into consideration. The window-address range must be specified within the GRAM address area. An address set must be set within the window-address range. [Condition on setting window-address range] (Horizontal direction) 00H HSA7-0 HSA7-0 AFH (Vertical direction) 00H VSA7-0 VEA7-0 EFH [Condition on making an address set within the window-address range] (RAM address) HSA7-0 AD7-0 HEA7-0 VSA7-0 AD15-8 VEA7-0 Note: In high-speed RAM write mode, the lower two bits of the address must be set as follows. ID0=0: The lower two bits of the address must be set to 11. ID0=1: The lower two bits of the address must be set to 00.
GRAM address map "0000"H "00AF"H
Window address area "2010"H "2110"H "202F"H "212F"H
"5F10"H
"5F2F"H
"EF00"H Window address range specification area HSA7-0 = "10"H, HSE7-0 = "2F"H I/D = 1 (increment) VSA7-0 = "20"H, VEA7-0 = "5F"H AM = 0 (horizontal writing)
"EFAF"H
Address transition direction in specified window-address range
Rev.0.22, May.23.2003, page 110 of 159
HD66787
Preliminary
Graphics Operation Function
The HD66787 greatly reduces the load on the graphics-processing software in the microcomputer with the 18-bit bus architecture and the graphics bit operation. The graphics bit operation includes: 1. The write data mask function that selectively rewrites some bits of 18-bit write data. 2. The conditional rewrite function that compares the write data and the compare bit data and writes the data sent from the microcomputer only when the conditions are satisfied. The graphics bit operation is controlled by setting bits in the entry mode register and RAM-write-data mask register, and the write operation from the microcomputer. Graphics Operation
Bit Setting Operation Mode Write mode 1 Write mode 2 Write mode 3 Write mode 4 I/D 0/1 0/1 0/1 0/1 AM 0 1 0 1 LG2-0 000 000 110 111 110 111 Operation and Usage Horizontal data replacement Vertical data replacement Conditional horizontal data replacement Conditional vertical data replacement
Microcomputer
18
Write data latch
18 +1/-1 +256 3
Address counter (AC)
Logical/Compare operation (LG2-0) 000: replacement 110: replacement with matched write 111: replacement with unmatched write
18
Logical operation bit (LG2-0) Compare bit (CP17-0)
18
18
Write bit mask
16
Write-mask register (WM17-0)
Graphics RAM (GRAM)
Graphics operation flow
Rev.0.22, May.23.2003, page 111 of 159
HD66787 Write-data Mask Function
Preliminary
The HD66787 expands the 16-bit data sent from the microcomputer into the 18-bit data. In the18-bit interface mode, data are not expanded. The write data mask function of the HD66787 controls the write operation of the 18-bit data from the microcomputer to GRAM by bit. The write data mask function write data in the bits whose corresponding bits in the write data mask resister (WM17-0) are assigned with "0" and does not write data in the bits whose corresponding bits in the write data mask register (WM17-0) are assigned with "1", and the corresponding data in GRAM are not overwritten but retained. This function is useful when only one-pixel data are rewritten or a particular color in the display is selectively changed.
DB17 Data from the microcomputer DB0
R05 R04 R03 R02 R01 R00 G05 G04 G03 G02 G02 G01 G00 B05 B04 B03 B02 B01 B00
WM17 Write data mask 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0
WM0 0
17 GRAM data
0 G05 G04 G03 G02 G02 G01 G00
******
****
B01 B00
Note : Data are expanded into 18 bits in the 8/16-bit system interface and the 16 RGB interface modes.
Write data mask function Graphics Operation Processing Examples 1. Write mode 1: AM = 0, LG2-0 = 000 This mode is used when data are horizontally written in high speed mode. It is also used to initialize the graphics RAM (GRAM) or to draw a line horizontally. The write-data mask function (WM17-0) is also available in these operations. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next one-raster-row below after when the counter reaches either left or right edge of GRAM.
Operation example 1) I/D = "1", AM = "0", LG2-0 = "000" 2) WM17-0 = "00FFF"H 3) AC = "0000"H
WM17 WM0
Write-data mask:
000000111111111111 DB17 DB0
*Write-mask , planes.
Write-data (1) Write-data (2)
100111111100101000 110001000001100000
Data are expanded into 18 bits in 8/16-bit system interface, and 16-bit RGB interface modes.
"0000"H
" 0001" H
" 0002"H
100111 * * * * * * * * * * * * 110001 * * * * * * * * * * * *
Write data (1) Write data (2) Note : The bits in the GRAM with " *" " are not overwritten.
GRAM
Write Mode 1
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HD66787 2. Write mode 2: AM = 1, LG2-0 = 000
Preliminary
This mode is used when data are vertically written in high speed mode. It is also used to initialize the graphics RAM (GRAM), develop font patterns or to draw a line vertically. The write-data mask function (WM17-0) is also available in these operations. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (ID = 1) or at the top of the next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the bottom of GRAM.
Operation example 1) I/D = "1", AM = "1", LG2-0 = "000" 2) WM17-0 = "00FFF"H 3) AC = "0000"H WM17 Write-data mask: WM0
000000111111111111
DB17 DB0
Write-data (1): Write-data (2): Write-data (3):
100111111100101000 110001000001100000 011110100010000011
Data are expanded into 18 bits in 8/16-bit system interface, and 16-bit RGB interface modes.
"0000"H "0001"H "0002"H
100111 * * * * * * * * * * * * 110001 * * * * * * * * * * * * 011110 * * * * * * * * * * * *
Write-data (1) Write-data (2) Write-data (3)
GRAM
Note 1) The bits in the GRAM with "are not overwritten. * " Note 2) After writing data to the address "EF00"H, the address counter jumps to "0001"H.
Write Mode 2
Rev.0.22, May.23.2003, page 113 of 159
HD66787
Preliminary
3. Write mode 3: AM = 0, LG2-0 = 110/111 This mode is used when data are horizontally written with comparing the write data and the value set in the compare register (CP17-0) by R, G, B pixel. When the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to GRAM. In this operation, the write-data mask function (WM17-0) is available. After writing, the address counter (AC) automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and jumps to the counter at the opposing edge of the next oneraster-row below after when the counter reaches either left or right edge of GRAM.
Operation example 1) I/D = "1", AM = "0", LG2-0 = "110" (matched writing) 2)CP17-0 = "050C0"H 3)WM17-0 = "00000"H 4) AC = "0000"H WM17 Write-data mask: WM0
000000000000000000
CP17 CP0 Compare operation
Compare register:
000101000011000000
DB17 (Matched) DB0
Conditional replacement
Write-data (1):
000101000011000000 C
Compare operation
R
000101000011000000
Replacement
Conditional replacement
Write-data (2):
000000111111000000
Data are expanded into 18 bits in 8/16-bit system interface, and 16-bit RGB interface modes.
C
R
******************
"0000"H
"0001"H
000101000011000000 * * * * * * * * * * * * * * * * * *
write data (1) matched replacement
GRAM
Write Mode 3
Rev.0.22, May.23.2003, page 114 of 159
HD66787
Preliminary
4. Write mode 4: AM = 1, LG2-0 = 110/111 This mode is used when data are horizontally written with comparing the write data and the value set in the compare register (CP17-0) by R, G, B pixel. When the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to GRAM. In this operation, the write-data mask function (WM17-0) is available. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the counter either at the top of the next right row (ID = 1) or at the top of the next left row (I/D = 0) according to the setting in the I/D bit, when the address reaches the bottom of GRAM.
Operation example 1) I/D = "1", AM = "1", LG2-0 = "111" (unmatched writing) 2)CP17-0 = "0A0C0"H 3)WM17-0 = "00000"H 4) AC = "0000"H WM17 Write-data mask: WM0
000000000000000000
CP17 CP0 Compare operation
Compare register:
001010000011000000
DB17 ( Unmatched) DB0
Conditional replacement
Write-data (1):
100111001100111111 C
(Matched) Compare operation
R
100111001100111111
Replacement
Conditional replacement
Write-data (2):
001010000011000000
C
R
******************
Data are expanded into 18 bits in 8/16-bit system interface, and 16-bit RGB interface modes.
"0000"H
"0100"H
"0000"H 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 Write-data (1) "0100"H
******************
Write-data (2)
"EF00"H
GRAM
Note 1) The bits in the GRAM with "are not overwritten. * " Note 2) After writing data to the address "EF00"H, the address counter jumps to "0001"H.
Write Mode 4
Rev.0.22, May.23.2003, page 115 of 159
HD66787
Preliminary
-Correction Function
The HD66787 incorporates -correction function to simultaneously display 262,144 colors, by which 8level grayscale is determined by the gradient-adjustment and fine-adjustment registers. Select either positive or negative polarity of the registers according to the characteristics of a liquid crystal panel.
MSB Display data
Graphics RAM(GRAM)
LSB
R5
R4
R3
R2
R1
R0
G5 G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
PKP 02 PKP 01 PKP 00 PKP 12 PKP 11 PKP 10
Positive Polarity Register
PKP 22 PKP 21 PKP 20 PKP 32 PKP 31 PKP 30 PKP 42 PKP 41 PKP 40 PKP 52 PKP 51 PKP 50 PRP 02 PRP 01 PRP 00
V0
6
6
6
Grayscale Amplifier
PRP 12 PRP 11 PRP 10 VRP 03 VRP 02 VRP 01 VRP00 VRP 14 VRP 13 VRP 12 VRP 11 VRP10 PKN 02 PKN 01 PKN 00 PKN 12 PKN 11 PKN 10
V1 32
32-level grayscale control FRC control 32-level grayscale control FRC control LCD driver 32-level grayscale control FRC control LCD driver
8
V31
LCD driver
Negative Polarity Register
PKN 22 PKN 21 PKN 20 PKN 32 PKN 31 PKN 30 PKN 42 PKN 41 PKN 40 PKN 52 PKN 51 PKN 50 PRN 02 PRN 01 PRN 00 PRN 12 PRN 11 PRN 10
VRN 03 VRN 02 VRN01 VRN00 VRN14 VRN13 VRN12 VRN11 VRN10
RGB
LCD
Grayscale control
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HD66787 Configuration of Grayscale Amplifier
Preliminary
The eight levels (VIN0-7) of grayscale are determined by the gradient adjustment and fine adjustment registers. The 8 levels are then divided into 32 levels (V0-31) by the ladder resistors placed between each level.
Grayscale amplifier
Rev.0.22, May.23.2003, page 117 of 159
HD66787
Preliminary
VDH
VRP0 0 ~30R 5R
RP0 RP1 RP2 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8
VRP0[3:0]
KVP0
VINP 0 i PKP0[2:0]
VRN0 0 ~30R 5R
VRN0[3:0]
KVN0
VINN0 PKN0[2:0]
RN0 KVN1 RN1 RN2 KVN2 KVN3 KVN4 8 to 1 KVN5 SE L L KVN6 KVN7 KVN8
4R
RP3 RP4 RP5 RP6 RP7
8 to 1 SE L L
VINP1 i
4R
RN3 RN4 RN5 RN6 RN7
VINN1
VRHP 0 ~28R
RP8 RP9 RP10 RP11 RP12 RP13 RP14
PRP0[2:0]
KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16
PKP1[2:0]
VRHN 0 ~28R
RN8 RN9 RN10 RN11 RN12 RN13 RN14 RN15 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25
PRN0[2:0]
KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16
PKN1[2:0]
1R
8 to 1 SE L L
VINP 2 I
1R
8 to 1 SE L L
VINN2
5R
RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24
PKP2[2:0]
5R
PKN2[2:0]
KVN17 KVN18 KVN19 KVN20 KVN21 8 to 1 KVN22 SE L L KVN23 KVN24
1R
8 to 1 SE L L
VINP3 I
1R
VINN3
16R
PKP3[2:0]
16R
PKN3[2:0]
KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32
1R
RP26 RP27 RP28 RP29 RP30
8 to 1 SE L L
VINP4 I
1R
RN26 RN27 RN28 RN29 RN30
8 to 1 SE L L
VINN4
5R
RP31 KVP33 RP32 RP33 RP34 RP35 RP36 RP37 RP38 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40
PKP4[2:0]
5R
RN31 KVN33 RN32 RN33 RN34 RN35 RN36 RN37 RN38 KVN34 KVN35 KVN36 8 to 1 KVN37 SE L L KVN38 KVN39 KVN40
PKN4[2:0]
1R
8 to 1 SE L L
VINP 5 I
VINN5
VRLP 0~28R
RP39 RP40 RP41 RP42 RP43 RP44 RP45
PRP1[2:0]
KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48
PKP5[2:0]
VRLN 0 ~28R
RN39 RN40 RN41 RN42 RN43 RN44 RN45
PRN1[2:0]
KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48
PKN5[2:0]
4R
8 to 1 SE L L
VINP 6 I
4R
8 to 1 SE L L
VINN6
5R VRP1 0~31R VGS 8R
RP46 KVP49 VRP1[4:0] RP47 VINP 7 I
5R VRN 0~31R 8R
RN46 KVN49 VRN1[4:0] RN47 VINN7
Ladder Resistors and 8-to-1 Selectors
Rev.0.22, May.23.2003, page 118 of 159
HD66787 -Correction Register
Preliminary
The -adjustment register is a group of registers to set an appropriate grayscale voltage for the characteristics of a liquid crystal panel. The register group is categorized into the ones adjusting gradient, amplitude, and fine-tuning in relation to grayscale number and grayscale voltage characteristics. Each register can make an independent setting for the positive/negative polarity. The reference value and RGB are common to both polarities.
Glayscale voltage
Glayscale voltage
Grayscale number
Grayscale number
Glayscale voltage
Grayscale number
Gradient adjustment
Amplitude adjustment
Fine adjustment
Gradient, Amplitude, Fine Adjustments 1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient around the middle of the grayscale number and voltage characteristics without changing a dynamic range. To adjust a gradient, the values of the variable resistors (VRHP (N)/VRLP (N)) in the ladder resistor block for grayscale voltage generation are controlled. The registers incorporate separate registers for positive and negative polarities to be compatible with asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. To adjust the amplitude, the values of the variable resistors (VRP(N)1/0) in the bottom of the ladder resistor block for grayscale voltage generation are adjusted. Same with the gradient registers, the amplitude adjustment registers also incorporate separate registers for positive and negative polarities. 3. Fine adjustment registers The fine adjustment register is to fine-adjust the grayscale voltage level. To fine-adjust the grayscale voltage level, each level of 8-level reference voltages generated from the ladder registers is controlled by 8to-1 selector. Same with the other registers, the fine adjustment registers also incorporate separate registers for positive and negative polarities.
Rev.0.22, May.23.2003, page 119 of 159
HD66787 -Correction Registers
Register Groups Gradient adjustment Amplitude adjustment Fine adjustment Positive Polarity PRP0 2 to 0 PRP1 2 to 0 VRP0 3 to 0 VRP1 4 to 0 PKP0 2 to 0 PKP1 2 to 0 PKP2 2 to 0 PKP3 2 to 0 PKP4 2 to 0 PKP5 2 to 0 Negative Polarity PRN0 2 to 0 PRN1 2 to 0 VRN0 3 to 0 VRN1 4 to 0 PKN0 2 to 0 PKN1 2 to 0 PKN2 2 to 0 PKN3 2 to 0 PKN4 2 to 0 PKN5 2 to 0 Description Variable resistor VRHP (N) Variable resistor VRLP (N) Variable resistor VRP (N)0 Variable resistor VRP (N)1
Preliminary
8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62)
Ladder resistors and 8-to-1 selector Block configuration The block diagram of page 117 consists of two ladder resistors including variable resistors, and 8-to-1 selectors which select the voltage generated by the ladder resistors to output a reference voltage for the grayscale voltage. The variable resistors and the 8-to-1 selectors are controlled by the correction registers. Pins that are connected to a variable resistor are also provided to compensate the variation among the panels. Variable resistor There are three kinds of variable resistors for the gradient adjustment (VRHP(N)/VRLP(N)), the amplitude adjustment (1) (VRP(N)0), and the amplitude adjustment (2) (VRP(N)1). The resistance is determined by the gradient adjustment and amplitude adjustment registers as is shown below. Gradient adjustment
Contents of Register PRP(N) 0/1[2:0] Resistance VRHP(N) VRLP(N)
Amplitude adjustment (1)
Contents of Register VRP(N)0[3:0] Resistance VRP(N)0
Amplitude adjustment (2)
Contents of Register VRP(N)1[4:0] Resistance VRP(N)1
000 001 010 011 100 101 110 111
0R 4R 8R 12R 16R 20R 24R 28R
0000 0001 0010 * * * * 1101 1111 1111
0R 2R 4R * * * * 26R 28R 30R
00000 00001 00010 * * * * 11101 11110 11111
0R 1R 2R * * * * 29R 30R 31R
Rev.0.22, May.23.2003, page 120 of 159
HD66787 8-to-1 selector
Preliminary
The 8-to-1 selectors select a voltage level generated by the ladder resistors according to fine adjustment registers, and output six kinds of reference voltage, VIN1 to VIN 6. The relationship between the fine adjustment register and the selected voltage is as follows. Fine adjustment registers and selected voltage
The value of Register PKP(N)[2:0] 000 001 010 011 100 101 110 111 Selected Voltage VINP(N)1 KVP(N)1 KVP(N)2 KVP(N)3 KVP(N)4 KVP(N)5 KVP(N)6 KVP(N)7 KVP(N)8 VINP(N)2 KVP(N)9 KVP(N)10 KVP(N)11 KVP(N)12 KVP(N)13 KVP(N)14 KVP(N)15 KVP(N)16 VINP(N)3 KVP(N)17 KVP(N)18 KVP(N)19 KVP(N)20 KVP(N)21 KVP(N)22 KVP(N)23 KVP(N)24 VINP(N)4 KVP(N)25 KVP(N)26 KVP(N)27 KVP(N)28 KVP(N)29 KVP(N)30 KVP(N)31 KVP(N)32 VINP(N)5 KVP(N)33 KVP(N)34 KVP(N)35 KVP(N)36 KVP(N)37 KVP(N)38 KVP(N)39 KVP(N)40 VINP(N)6 KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48
Rev.0.22, May.23.2003, page 121 of 159
HD66787 The grayscale levels (V0-V31) are calculated according to the following formulas. Formulas for calculating voltage (Positive polarity) (1)
Reference Voltage
Preliminary
Pin
KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49
Formula
VREG1OUT - V*VRP0/SUMRP VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT VREG1OUT - V* VRP0+5R)/SUMRP - V* VRP0+9R)/SUMRP - V* VRP0+13R)/SUMRP - V* VRP0+17R)/SUMRP - V* VRP0+21R)/SUMRP - V* VRP0+25R)/SUMRP - V* VRP0+29R)/SUMRP - V* VRP0+33R)/SUMRP - V*(VRP0+33R+VRHP)/SUMRP - V*(VRP0+34R+VRHP)/SUMRP - V*(VRP0+35R+VRHP)/SUMRP - V*(VRP0+36R+VRHP)/SUMRP - V*(VRP0+37R+VRHP)/SUMRP - V*(VRP0+38R+VRHP)/SUMRP - V*(VRP0+39R+VRHP)/SUMRP - V*(VRP0+40R+VRHP)/SUMRP - V*(VRP0+45R+VRHP)/SUMRP - V*(VRP0+46R+VRHP)/SUMRP - V*(VRP0+47R+VRHP)/SUMRP - V*(VRP0+48R+VRHP)/SUMRP - V*(VRP0+49R+VRHP)/SUMRP - V*(VRP0+50R+VRHP)/SUMRP - V*(VRP0+51R+VRHP)/SUMRP - V*(VRP0+52R+VRHP)/SUMRP - V*(VRP0+68R+VRHP)/SUMRP - V*(VRP0+69R+VRHP)/SUMRP - V*(VRP0+70R+VRHP)/SUMRP - V*(VRP0+71R+VRHP)/SUMRP - V*(VRP0+72R+VRHP)/SUMRP - V*(VRP0+73R+VRHP)/SUMRP - V*(VRP0+74R+VRHP)/SUMRP - V*(VRP0+75R+VRHP)/SUMRP - V*(VRP0+80R+VRHP)/SUMRP - V*(VRP0+81R+VRHP)/SUMRP - V*(VRP0+82R+VRHP)/SUMRP - V*(VRP0+83R+VRHP)/SUMRP - V*(VRP0+84R+VRHP)/SUMRP - V*(VRP0+85R+VRHP)/SUMRP - V*(VRP0+86R+VRHP)/SUMRP - V*(VRP0+87R+VRHP)/SUMRP - V*(VRP0+87R+VRHP+VRLP)/SUMRP - V*(VRP0+91R+VRHP+VRLP)/SUMRP - V*(VRP0+95R+VRHP+VRLP)/SUMRP - V*(VRP0+99R+VRHP+VRLP)/SUMRP - V*(VRP0+103R+VRHP+VRLP)/SUMRP - V*(VRP0+107R+VRHP+VRLP)/SUMRP - V*(VRP0+111R+VRHP+VRLP)/SUMRP - V*(VRP0+115R+VRHP+VRLP)/SUMRP - V*(VRP0+120R+VRHP+VRLP)/SUMRP
Fine adjustment register value
PKP02-00 = "000" PKP02-00 = "001" PKP02-00 = "010" PKP02-00 = "011" PKP02-00 = "100" PKP02-00 = "101" PKP02-00 = "110" PKP02-00 = "111" PKP12-10 = "000" PKP12-10 = "001" PKP12-10 = "010" PKP12-10 = "011" PKP12-10 = "100" PKP12-10 = "101" PKP12-10 = "110" PKP12-10 = "111" PKP22-20 = "000" PKP22-20 = "001" PKP22-20 = "010" PKP22-20 = "011" PKP22-20 = "100" PKP22-20 = "101" PKP22-20 = "110" PKP22-20 = "111" PKP32-30 = "000" PKP32-30 = "001" PKP32-30 = "010" PKP32-30 = "011" PKP32-30 = "100" PKP32-30 = "101" PKP32-30 = "110" PKP32-30 = "111" PKP42-40 = "000" PKP42-40 = "001" PKP42-40 = "010" PKP42-40 = "011" PKP42-40 = "100" PKP42-40 = "101" PKP42-40 = "110" PKP42-40 = "111" PKP52-50 = "000" PKP52-50 = "001" PKP52-50 = "010" PKP52-50 = "011" PKP52-50 = "100" PKP52-50 = "101" PKP52-50 = "110" PKP52-50 = "111" -
VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
SUMRP : Sum of positive ladder resistors = 128R+VRHP+VRLP+VRP0+VRP1 SUMRN : Sum of negative ladder resistors = 128R+VRHN+VRLN+VRN0+VRN1 V : Voltage difference between VREG1OUT and VGS
Rev.0.22, May.23.2003, page 122 of 159
HD66787 Formulas for calculating voltage (Positive polarity) (2)
Preliminary
Grayscale Voltage
Formula VINP0 V4+(VINP1-V4)*(15/24) V4+(VINP1-V4)*(8/24) V4+(VINP1-V4)*(4/24) VINP2 V10+(V4-V10)*(20/24) V10+(V4-V10)*(16/24) V10+(V4-V10)*(12/24) V10+(V4-V10)*(8/24) V20+(V8-V20)*(4/24) VINP3 V21+(V10-V21)*(21/24) V21+(V10-V21)*(19/24) V21+(V10-V21)*(17/24) V21+(V10-V21)*(15/24) V21+(V10-V21)*(13/24) V21+(V10-V21)*(11/24) V21+(V10-V21)*(9/24) V21+(V10-V21)*(7/24) V21+(V10-V21)*(5/24) V21+(V10-V21)*(3/24) VINP4 V27+(V21-V27)*(20/24) V27+(V21-V27)*(16/24) V27+(V21-V27)*(12/24) V27+(V21-V27)*(8/24) V27+(V21-V27)*(4/24) VINP5 VINP6+(V27-VINP6)*(20/24) VINP6+(V27-VINP6)*(16/24) VINP6+(V27-VINP6)*(9/24) VINP7
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31
Note : Make sure DDVDH - V0 > 0.5V DDVDH - V4 > 1.1V
Rev.0.22, May.23.2003, page 123 of 159
HD66787 Formulas for calculating voltage (Negative polarity) (1)
Pin
KVP0 KVN1 KVN2 KVN3 KVN4 KVN 5 KVN 6 KVN 7 KVN 8 KVN9 KVN10 KVN 11 KVN 12 KVN13 KVN 14 KVN 15 KVN 16 KVN 17 KVN 18 KVN19 KVN 20 KVN 21 KVN22 KVN 23 KVN 24 KVN25 KVN 26 KVN 27 KVN28 KVN 29 KVN30 KVN31 KVN 32 KVN33 KVN34 KVN 35 KVN36 KVN37 KVN38 KVN 39 KVN40 KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49
Preliminary
Formula
VREG1OUT - V*VRN0/SUMRN VREG1OUT - V* VRN0+5R)/SUMRN VREG1OUT - V* VRN0+9R)/SUMRN VREG1OUT - V* VRN0+13R)/SUMRN VREG1OUT - V* VRN0+17R)/SUMRN VREG1OUT - V* VRN0+21R)/SUMRN VREG1OUT - V* VRN0+25R)/SUMRN VREG1OUT - V* VRN0+29R)/SUMRN VREG1OUT - V* VRN0+33R)/SUMRN VREG1OUT - V*(VRN0+33R+VRHN)/SUMRN VREG1OUT - V*(VRN0+34R+VRHN)/SUMRN VREG1OUT - V*(VRN0+35R+VRHN)/SUMRN VREG1OUT - V*(VRN0+36R+VRHN)/SUMRN VREG1OUT - V*(VRN0+37R+VRHN)/SUMRN VREG1OUT - V*(VRN0+38R+VRHN)/SUMRN VREG1OUT - V*(VRN0+39R+VRHN)/SUMRN VREG1OUT - V*(VRN0+40R+VRHN)/SUMRN VREG1OUT - V*(VRN0+45R+VRHN)/SUMRN VREG1OUT - V*(VRN0+46R+VRHN)/SUMRN VREG1OUT - V*(VRN0+47R+VRHN)/SUMRN VREG1OUT - V*(VRN0+48R+VRHN)/SUMRN VREG1OUT - V*(VRN0+49R+VRHN)/SUMRN VREG1OUT - V*(VRN0+50R+VRHN)/SUMRN VREG1OUT - V*(VRN0+51R+VRHN)/SUMRN VREG1OUT - V*(VRN0+52R+VRHN)/SUMRN VREG1OUT - V*(VRN0+68R+VRHN)/SUMRN VREG1OUT - V*(VRN0+69R+VRHN)/SUMRN VREG1OUT - V*(VRN0+70R+VRHN)/SUMRN VREG1OUT - V*(VRN0+71R+VRHN)/SUMRN VREG1OUT - V*(VRN0+72R+VRHN)/SUMRN VREG1OUT - V*(VRN0+73R+VRHN)/SUMRN VREG1OUT - V*(VRN0+74R+VRHN)/SUMRN VREG1OUT - V*(VRN0+75R+VRHN)/SUMRN VREG1OUT - V*(VRN0+80R+VRHN)/SUMRN VREG1OUT - V*(VRN0+81R+VRHN)/SUMRN VREG1OUT - V*(VRN0+82R+VRHN)/SUMRN VREG1OUT - V*(VRN0+83R+VRHN)/SUMRN VREG1OUT - V*(VRN0+84R+VRHN)/SUMRN VREG1OUT - V*(VRN0+85R+VRHN)/SUMRN VREG1OUT - V*(VRN0+86R+VRHN)/SUMRN VREG1OUT - V*(VRN0+87R+VRHN)/SUMRN VREG1OUT - V*(VRN0+87R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+91R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+95R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+99R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+103R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+107R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+111R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+115R+VRHN+VRLP)/SUMRN VREG1OUT - V*(VRN0+120R+VRHN+VRLP)/SUMRN
Fine adjustment register value
Reference Voltage
PKN 02-00 = "000" PKN 02-00 = "001" PKN 02-00 = "010" PKN 02-00 = "011" PKN 02-00 = "100" PKN 02-00 = "101" PKN 02-00 = "110" PKN 02-00 = "111" PKN 12-10 = "000" PKN 12-10 = "001" PKN 12-10 = "010" PKN 12-10 = "011" PKN 12-10 = "100" PKN 12-10 = "101" PKN 12-10 = "110" PKN 12-10 = "111" PKN 22-20 = "000" PKN 22-20 = "001" PKN 22-20 = "010" PKN 22-20 = "011" PKN 22-20 = "100" PKN 22-20 = "101" PKN 22-20 = "110" PKN 22-20 = "111" PKN 32-30 = "000" PKN 32-30 = "001" PKN 32-30 = "010" PKN 32-30 = "011" PKN 32-30 = "100" PKN 32-30 = "101" PKN 32-30 = "110" PKN 32-30 = "111" PKN 42-40 = "000" PKN 42-40 = "001" PKN 42-40 = "010" PKN 42-40 = "011" PKN 42-40 = "100" PKN 42-40 = "101" PKN 42-40 = "110" PKN 42-40 = "111" PKN 52-50 = "000" PKN 52-50 = "001" PKN 52-50 = "010" PKN 52-50 = "011" PKN 52-50 = "100" PKN 52-50 = "101" PKN 52-50 = "110" PKN 52-50 = "111" -
VINN0
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
SUMRP : Sum of positive ladder resistors = 128R+VRHP+VRLP+VRP0+VRP1 SUMRN : Sum of negative ladder resistors = 128R+VRHN+VRLN+VRN0+VRN1 V: Voltage difference between VREG1OUT and VGS
Rev.0.22, May.23.2003, page 124 of 159
HD66787 Formulas for calculating voltage (Negative polarity) (2)
Grayscale Voltage
Preliminary
Formula
V0 VINN0 V1 V4+(VINN1-V4)*(15/24) V2 V4+(VINN1-V4)*(8/24) V3 V4+(VINN1-V4)*(4/24) V4 VINN2 V10+(V4-V10)*(20/24) V5 V6 V10+(V4-V10)*(16/24) V7 V10+(V4-V10)*(12/24) V8 V10+(V4-V10)*(8/24) V20+(V8-V20)*(4/24) V9 VINN3 V10 V11 V21+(V10-V21)*(21/24) V12 V21+(V10-V21)*(19/24) V13 V21+(V10-V21)*(17/24) V21+(V10-V21)*(15/24) V14 V21+(V10-V21)*(13/24) V15 V21+(V10-V21)*(11/24) V16 V21+(V10-V21)*(9/24) V17 V21+(V10-V21)*(7/24) V18 V21+(V10-V21)*(5/24) V19 V20 V21+(V10-V21)*(3/24) V21 VINN4 V27+(V21-V27)*(20/24) V22 V27+(V21-V27)*(16/24) V23 V27+(V21-V27)*(12/24) V24 V27+(V21-V27)*(8/24) V25 V27+(V21-V27)*(4/24) V26 V27 VINN5 V28 VINN6 +(V27-VINN6)*(20/24) V29 VINN6 +(V27-VINN6)*(16/24) V30 VINN6 +(V27-VINN6)*(9/24) VINN7 V31 Note : Make sure DDVDH - V0 > 0.5V DDVDH - V4 > 1.1V
Rev.0.22, May.23.2003, page 125 of 159
HD66787 Relationship between RAM data and output level The relationship between the RAM data and the source output level is as follows.
V0 Negative polarity
Preliminary
Positive polarity V31
000000
RAM data
(Common for each RGB pixel)
RAM data and the output voltage
Sn
Negative polarity Vcom Positive polarity
Source output and Vcom
Rev.0.22, May.23.2003, page 126 of 159
111111
HD66787
Preliminary
8-color Display Mode
The HD66787 incorporates the 8-color display mode. The available grayscale levels are V0 and V31, and the voltages for the other levels (V1-V30) are halted to reduce power consumption. The -fine-adjustment registers, PKP0-PKP5 and PKN0-PKN5 are not available in the 8-color display mode. Since the power supply for the levels V1-V30 are halted, RGB data in GRAM should be set to either "000000" or "111111" before setting this mode so that V0 or V31 is selected.
MSB Display data
Graphics RAM(GRAM)
LSB
R5
R4
R3
R2
R1
R0
G5 G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
PKP 02 PKP 01 PKP 00 PKP 12 PKP 11 PKP 10
Positive Polarity Register
PKP 22 PKP 21 PKP 20 PKP 32 PKP 31 PKP 30 PKP 42 PKP 41 PKP 40 PKP 52 PKP 51 PKP 50 PRP 02 PRP 01 PRP 00
V0
6
6
6
Grayscale Amplifier
PRP 12 PRP 11 PRP 10 VRP 03 VRP 02 VRP 01 VRP00 VRP 14 VRP 13 VRP 12 VRP 11 VRP10 PKN 02 PKN 01 PKN 00 PKN 12 PKN 11 PKN 10
8
2
2 - level grayscale control
2 - level grayscale control
2 - level grayscale control
V31
LCD driver
LCD driver
Negative Polarity Register
PKN 22 PKN 21 PKN 20 PKN 32 PKN 31 PKN 30 PKN 42 PKN 41 PKN 40 PKN 52 PKN 51 PKN 50 PRN 02 PRN 01 PRN 00 PRN 12 PRN 11 PRN 10
LCD driver
VRN 03 VRN 02 VRN01 VRN00 VRN14 VRN13 VRN12 VRN11 VRN10
RGB
LCD
Grayscale control
Rev.0.22, May.23.2003, page 127 of 159
HD66787
Preliminary
To switch between the 262, 144-color mode and the 8-color mode, make settings according to the following sequences.
262,144 to 8 colors Display off DTE = "1" D1-0 = "10" Wait (2 frame or more) Display off DTE = "0" D1-0 = "10" Wait (2 frame or more) Display off DTE = "0" D1-0 = "00"
8 to 22,144 colors Display off DTE = "1" D1-0 = "10" Wait (2 frame or more) Display off DTE = "0" D1-0 = "10" Wait (2 frame or more) Display off DTE = "0" D1-0 = "00"
Setting of RAM CL = "1" Wait (40 msec or more) Display on DTE = "0" D1-0 = "01" Wait (2 frame or more)
Setting of RAM CL = "0" Wait (40 msec or more) Display on DTE = "0" D1-0 = "01" Wait (2 frame or more)
Display on DTE = "0" D1-0 = "11" Wait (2H or longer) Display on DTE = "1" D1-0 = "11" Displaying in 8-color mode
Display on DTE = "0" D1-0 = "11" Wait (2H or longer) Display on DTE = "1" D1-0 = "11" Displaying in 262,144-color mode
Rev.0.22, May.23.2003, page 128 of 159
HD66787
Preliminary
System Configuration
The following figure illustrates an example of configuring a TFT-LCD panel of 176x 240 dots withHD66787.
176 pixels x 3
, VGH,VGL
G1 G2
Shift register
LTPS- TFT
G239 G240
240
SOUT1 SOUT2 SOUT3 SOUT4
4
Driver circuits for incorporated gates
S1S2
S527 S528
Vcom
Power supply circuit Vcom LevelShift DCDC
VGH,VGL
HD66787
Vci1 Vci
18
4
3
18
4
Vcc GND
RESET DB0
~17
IM2,IM1, VLD PD0 ~17 IM0/ID VS HS DO EN
CS*,WR*, RD*, RS
System configuration with HD66787
Rev.0.22, May.23.2003, page 129 of 159
HD66787
Preliminary
Configuration of Power Generation Circuit
The internal configuration of power generation circuit for driving liquid crystal with the HD66787 is as follows.
Separate on FPC in case of COG assembly
VREG1OUT
SOUT22 SOUT24 SOUT12 SOUT14 SOUT21 SOUT23 SOUT11 SOUT13
VciLVL
Voltage adjsutment circuit
Amplifier 1 Level Shifter
VcomH voltage adjsutment adjustment external variable l resistors) In case of using VciOUT AMP
REGP Vci VciOUT VcomR Vci1 C11VcomH Adjustment Circuit VciOUT AMP
LSEL12 LSEL11 LSEL10 LSEL22 LSEL21 LSEL20
Adjustment
circuit
Source Driver
Vci
C11+ VLOUT1
Step-up circuit 1
Grayscale voltage generation circuit
V0P V0N V31P V31N VMONI
Note 2)
DDVDH C12C12+ C21C21+ C22-
VcomH Output AMP
VcomH Vcom
Note 2)
Vci
C22+ VLOUT2 VGH VLOUT3 VGL Note 2,3) VLOUT4 Note 4) VCL Step-up circuit 2
Vcom amplitude adjustment circuit
VcomL Output AMP
VcomL TESTA1 TESTA2 TESTA4 Note 1)
HD66787
Vcc GND
Note 1) Connect stabilizing capacitors to the TESTTA1, TEST 2, and TESTA4 panel as required for the display quality of the panel and voltage consumption (0.1F, characteristic B). Otherwise, adopt 1F, characteristic B. Note 2) Place a shot-key diode (VF = about 0.4V/20mA, VR >=30V). Note 3) Wiring from GND or VGL to the shot-key dioode must be 10 or less. Note 4) Capacitors are not required when VCOMG = 0 (VCOML = GND).
Power generation circuit
Rev.0.22, May.23.2003, page 130 of 159
HD66787
Preliminary
Specification of External Elements Connected to HD66787 Power Supply
The following table shows specifications of external elements connected to HD66787 power supply. Capacitor
Capacity 1 F (B characteristic) Recommended voltage 6V 10V 25V 0.1 F (B characteristic) 6V Connect pins VREG1OUT, VciOUT, VOUT4, VcomH, VcomL, C11+/-, C21+/VLOUT1, C21+/-, C22+/VLOUT2, VLOUT3 V0P, V0N, V31P, V31N, TESTA4
Shot-key diode
Feature VF < 0.4V / 20mA at 25 centigrade, VR>=30V (recommended diode : HSC226) Connect pin GND - VGL (Vci - VGH) (Vci - DDVDH)
Variable resistor
Feature > 200 k Connect pin VcomR
Rev.0.22, May.23.2003, page 131 of 159
HD66787
Preliminary
Instruction Setting Flow
Make a setting for each instruction according to the following sequence. Display ON/OFF
Display on
Power supply setting
Display off
EQ = 0 Display off DTE = 1 D1-0 = 10 Wait (2 frames or more) Display off DTE = 0 D1-0 = 10
SAP2-0 Setting Display on DTE = 0 D1-0 = 01
Wait (2 frames or more)
Wait (2 frames or more) Display off DTE = 0 D1-0 = 00 Display on DTE = 0 D1-0 = 11
Power supply off SAP2-0 = "000" AP2-0 = "000" PON = "0" VCOMG = "0"
Wait (2 frames or more) Display on DTE = 1 D1-0 = 11
"Display on" "Display off" Display on flow Display off flow
Rev.0.22, May.23.2003, page 132 of 159
HD66787 Standby and Sleep
Standby
Display off flow
Preliminary
Sleep
Standby set
Display off low
Sleep set
Sleep set (SLP = "1")
Standby set (STB = "1")
Oscillation Start Wait 10 ms
Standby canceled (STB = "0")
Standby cancel
Sleep canceled (SLP = "0")
Sleep cancel
Power setting
Power setting
Display on flow Display on low
Rev.0.22, May.23.2003, page 133 of 159
HD66787
Preliminary
Power Supply Setting Flow
Whenever turning on the power supply, it must be done in accordance to the following procedure. The stabilization time for the oscillation circuits, step-up circuits, and operational amplifiers depends on the external resistors and capacitors.
Power supply (Vcc, Vci, IOVcc) ON
Vcc IOVcc Vci
GND Vcc(=RVcc) IOVcc Vci or Vcc(=RVcc), IOVcc, Vci Simultaneously
Normal Display
1ms or more
Bits for "Display ON" DTE = "1", D1-0="11"
Power ON RESET & Display OFF
Bits for "Display OFF" DTE="0", D1-0="00" PON="0" VCOMG="0"
10ms or more Oscillation Circuit Stabilization Time
Display OFF Sequence
Instructions for settings before driving Power Supply
Bits for Initializing Power Supply Settings VC2-0 bits setting VRH3-0 bits setting VCM4-0 bits setting VDV4-0 bits setting PON="0", DK="1" Bits for setting Power Supply Operation Start BT2-0="000" DC12-10 bits setting DC02-00 bits setting AP2-0 bits setting PON="1"
Display OFF
Bits for setting Power Supply Halt
Power supply setting Instruction (2)
Power Supply Instruction issue (1)
SAP2-0="000" AP2-0="000" PON="0" VCOMG="0"
Power Supply (Vcc, Vci, IOVcc) OFF
Vci IOVcc Vcc
40ms or more Step-up Circuit Stabilization Time
100ms or more
Power Supply Instruction issue (2)
Bits for setting Power Supply Operation Start VCOMG="1" BT2-0 bits setting DK="0"
Vci
IOVcc
GND Vcc(=RVcc) or
Vcc(=RVcc),IOVcc, Vci Simultaneously
Display OFF Sequence
Operational Amplifier Stabilization Time
Other mode settings Instruction issue
Display ON sequence
SAP2-0 bit setting
Display ON
Bits for "Display ON" DTE="1", D1-0="11"
Display ON Sequence
Power supply setting flow
Rev.0.22, May.23.2003, page 134 of 159
HD66787
Preliminary
Pattern Diagram for Voltage Setting
The following figures are the pattern diagram of voltage setting for the HD66787 and the voltage waveforms.
VLOUT2
VGH (+9 ~ +16.5V)
BT
VLOUT1
Vci (2.5 ~ 3.3V) Vcc (2.4 ~ 3.3V) IOVcc (1.8 ~ 3.3V) GND (0V)
DDVDH (4.5 ~ 5.5V) VREG1OUT (3.0 ~ (DDVDH-0.5)V)
VC
Vci1
VRH VDV
VcomH (3.0 ~ (DDVDH-0.5) V)
VCOMG VLOUT4 BT
VcomL ((VCL+0.5) ~ 1V)
VCL (0 ~ -3.3)V
VLOUT3
VGL (-4.0 ~ -16.5V)
Pattern diagram for voltage setting
Note 1) Voltage drop occurs in relation to set voltage for each DDVDH, VGH, VGL, VCL output depending on current consumption required for each output. (DDVDH+VREG1OUT) > 0.5V and (VcomL - VCL) > 0.5V show the relationship in relation to the actual voltage. When AC frequency of Vcom1 and Vcom2 is high (e.g. alternation occurs by line), current consumption is also large. In this case, check voltage before use.
VGH
Vcom Sn(Source driver output of HD66787) Gate Output
VDH VcomH VcomL
VGL
Applied voltage to the TFT display
Rev.0.22, May.23.2003, page 135 of 159
HD66787
Preliminary
Oscillation Circuit
The HD66787 generates oscillation by internal R-C oscillator with an external oscillation resistor placed between the OSC1 and OSC2 pins. The oscillation frequency varies depending on the value of external resistor, the distance of wiring, and the power supply voltage for the oscillation. For example, the oscillation frequency becomes low when increasing the value of Rf resistor, or lowering the power supply voltage. See the "Electric Characteristics Notes" section for the relationship between the Rf resistor value and the oscillation frequency.
OSC1 Rf OSC2 HD66787
OSC1 Rf OSC2 HD66787
External Resistor Oscillation Mode
Note 1) Place the Rf resistor close to the OSC1, OSC2 pins. Note 2) Make sure not to arrange other wiring beneath or close to OSC1-OSC2 wiring to avoid effects from coupling.
Rev.0.22, May.23.2003, page 136 of 159
HD66787
Preliminary
n-raster-row inversion AC drive
The HD66787, in addition to LCD inversion AC drive by frame, supports n-raster-row inversion AC drive where alternation occurs by n raster-rows, where n takes a number between 1 to 64. The n-raster-row inversion AC drive enables to overcome the problems related to display quality. In determining n (the value set in the NW bit +1), the number of raster-rows by which alternation occurs, check the display quality on the actual liquid crystal panel. Setting a small number of raster-rows will raise the AC frequency of the liquid crystal and increase the charge/discharge current on the liquid crystal cells.
1 frame Back porch 1 Frame AC driving 240-raster-row driving 2 3 4 Front porch Back porch 2 3 4 1 frame Front porch 241 242 256 1 2
241242
256 1
n-raster row driving 240-raster-row driving 3-raster-row reversed EOR = 1
Note: Make sure that EOR is set to "1" whenever the n-raster-row reverse AC driving to avoid DC bias.
n-raster-rows inversion AC drive
Rev.0.22, May.23.2003, page 137 of 159
HD66787
Preliminary
AC Timing
The AC timings of frame inversion AC drive and n-raster-row inversion drive are illustrated as follows. In case of frame inversion AC drive, alternation occurs at the completion of drawing one frame, followed by a blank, which lasts for 16H periods. In case of n-raster-row, a blank lasting 16H period is inserted after drawing a full screen.
n-raster-row inversion AC drive
AC timing Back porch Frame 1 AC timing AC timing AC timing AC timing AC timing AC timing AC timing AC timing AC timing Front porch AC timing Back porch
n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows n-raster-rows
Frame inversion AC drive
AC timing
One frame period
Front porch Blank period = 16H
Blank period = front porch + back porch = 16H
AC drive timing
Rev.0.22, May.23.2003, page 138 of 159
One frame period
HD66787
Preliminary
Frame-Frequency Adjustment Function
The HD66787 incorporates frame frequency adjustment function. The frame frequency during the liquid crystal drive is adjusted by the instruction setting (DIV, RTN) while keeping the oscillation frequency fixed. Setting the oscillation frequency high in advance allows switching the frame frequency in accordance to the kind of displayed picture (i.e. moving/still picture). When displaying a still picture, set the frame frequency low to save power consumption, while setting the frame frequency high when displaying a moving picture which requires high-speed switching of screens. Relationship between Liquid Crystal Drive Duty and Frame Frequency The relationship between the liquid crystal drive duty and the frame frequency is calculated by the following formula. The frame frequency is adjusted through the instruction setting with the 1-H period adjustment bit (RTN bit) and the operation clock division bit (DIV bit). (Formula for the frame frequency) fosc Frame frequency = Clock cycles per raster-row x division ratio x (Line+BP+FP) fosc: R-C oscillation frequency Line: number of drive raster-rows (NL bit) Clock cycles per raster-row: RTN bit Division ratio: DIV bit The number of raster-rows for the front porch: FP The number of raster-rows for the back porch: BP [Hz]
Calculation Example
The maximum frame frequency = 60 Hz
Number of driven raster-rows: 240 1-H period: 16 clock cycles (RTN3-0 = 0000) Operation clock division ratio: 1 division fosc = 60 Hz x (0 + 16) clock x 1 division x (240 + 16) lines = 246 (kHz) In this case, the R-C oscillation frequency becomes 246 kHz. Adjust the external resistor to the R-C oscillator to 246 kHz.
Rev.0.22, May.23.2003, page 139 of 159
HD66787
Preliminary
Screen-split Display Function
The HD66787 allows selectively driving two screens at arbitrary positions with the screen-drive position registers (R42 and R43). Only the raster-rows required to display two screens at arbitrary positions are selectively driven to reduce power consumption. The first screen drive position register (R42) specifies the start line (SS17-10) and the end line (SE17-10) for displaying the first screen. The second screen drive position register (R43) specifies the start line (SS27-20) and the end line (SE27-20) for displaying the second screen. The second screen control is effective when the SPT bit is set to 1. The total number of raster-rows driven for displaying the first and second screens must be less than the number of liquid crystal drive raster-rows.
G1 G7
1st Screen: 7 raster-row driving Non-display ar ea
G26 2nd Screen: 17 raster-row driving G42
Non-display ar ea
The number of driven raster-rows : NL4-0 = "11110" (240 raster-rows) 1st screen setting : SS17-10 = "00"H, SS17-10 = "06"H 2nd screen setting : SS27-20 = "19"H, SS27-20 = "29"H, SPT = "1"
Screen-split drive
Rev.0.22, May.23.2003, page 140 of 159
HD66787 Notes to the setting of 1st/2nd screen drive position registers
Preliminary
When making settings for the start line (SS17-10) and end line (SE17-10) of the first screen drive position register (R42), and the start line (SS27-20) and end line (SE27-20) of the second screen drive position register (R43) with the HD66787, it is necessary to satisfy the following conditions to display screens correctly. One Screen Drive (SPT = 0)
Register Settings (SE17-10) - (SS17-10) = NL (SE17-10) - (SS17-10) < NL Display Operation Full screen display The area of (SE17-10) - (SS17-10) is normally displayed. Partial screen display The area of (SE17-10) - (SS17-10) is normally displayed. The rest of the area is white display irrespective of data in RAM. Setting disabled
(SE17-10) - (SS17-10) > NL
Note 1) SS17-10 SE17-0 "EF"H Note 2) Setting disabled for SS27-20 and SE27-20.
Two Screen Drive (SPT = 1)
Register Settings ((SE17-10) - (SS17-10)) + ((SE27-20) - (SS27-20)) = NL ((SE17-10) - (SS17-10)) + ((SE27-20) - (S27-20)) < NL ((SE17-10) - (SS17-10)) + ((SE27-20) - (SS27-20)) > NL Display Operation Full screen display The area of (SE27-20) - (SS17-10) is normally displayed. Partial screen display The area of (SE27-10) - (SS17-10) is normally displayed. The rest of the area is white display irrespective of data in RAM. Setting disabled
Note 1) Make sure that SS17-10 SE17-10 < SS27-20 SE27-20 EFH. Note 2) Make sure that ((SE27-20) - (SS17-10)) NL.
The setting for the driver output in the non-display area during the partial display is changeable according to the characteristics of the display panel. Source outputs in non-display area
Source Output for Non-display Area PT1 0 0 1 1 PT0 0 1 0 1 Positive Polarity V31 V31 GND High-Z Negative Polarity V0 V0 GND High-Z
Rev.0.22, May.23.2003, page 141 of 159
HD66787
Full screen display
Preliminary
PT1-0 = 00
Set SS/SE bits
Wait for 2 screen or more
Screen division drive set up flow As required
PT1-0 = 01 or PT1-0 = 10 or PT1-0 = 11
Partial display ON Full screen display setting flow
Set SS/SE bits
Full screen display
Partial display setting flow
Rev.0.22, May.23.2003, page 142 of 159
HD66787
Preliminary
Absolute Maximum Values
Item Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Power supply voltage (4) Power supply voltage (5) Power supply voltage (6) Power supply voltage (7) Input voltage Operating temperature Storage temperature Symbol Vcc Vci - GND DDVDH - GND GND -VCL DDVDH - VCL VGH - GND GND - VGL Vt Topr Tstg Unit V V V V V V V V C C Value -0.3 ~ + 4.6 -0.3 ~ + 4.6 -0.3 ~ + 6.0 -0.3 ~ + 4.6 -0.3 ~ + 9.0 -0.3 ~ + 18.5 -0.3 ~ + 18.5 -0.3 ~ Vcc + 0.3 -40 ~ + 85 -55 ~ + 110 Notes 1, 2 1, 2 1, 2 1, 2 1 1, 2 1, 2 1 1, 3 1
Note 1) The LSI may be permanently damaged if it is used under the condition exceeding the above absolute maximum values. It is also recommended to use the LSI within the limit of its electric characteristics during normal operation. Exceeding the conditions may lead to malfunction of LSI and affect its credibility. Note 2) The voltage from GND. Note 3) The DC and AC characteristics of chip and wafer products are guaranteed at 85 C.
Rev.0.22, May.23.2003, page 143 of 159
HD66787
Preliminary
Electric Characteristics (T.B.D.)
DC Characteristics (VCC = 1.8 to 3.7 V, Ta = -40 to +85C Note 1 )
Item Input high voltage Input low voltage (1) (OSC1 pin) Input low voltage (2) (Except OSC1 pin) Symbol Unit Test Condition VIH VIL1 VIL2 V V V VCC = 1.8 to 3.7 V VCC = 1.8 to 3.7 V Vcc=1.8V to 2.4V Vcc=2.4V to 3.7V Output high voltage (1) (DB0-17 pins) Output low voltage (1) (DB0-17 pins) VOH1 V IOH = -0.1 mA VCC = 1.8 to 2.4 V, IOL = 0.1 mA VCC = 2.4 to 3.7 V, IOL = 0.1 mA I/O leakage current ILi A A Vin = 0 to VCC R-C oscillation; fosc = 250kHz (240line) VCC = 3.0 V, Ta = 25C, RAM data 0000h Vcc = 3V, Ta<=50C Vcc = 3V, Ta>50C Min Typ Max VCC Notes 2, 3
0.7 VCC -- -0.3 -0.3 -0.3 --
0.15VCC 2, 3 0.15Vc 2,3 c 0.2Vcc 2,3 -- 2
0.75VCC -- -- -- -1 -- -- -- -- 190
0.2 VCC 2 0.15VCC 2 1 300 4 5,6
VOL1
V
Current consumption IOP during normal operation (VCC - GND)
Current consumption during standby mode (VCC - GND) Liquid Crystal Power Current (DDVDH-GND)
IST
T.B.D
A -- -- A Vcc=3V, VLCD=5.5V, VDH=5.0V, CR Oscillation; fosc=250kHz(240line), Ta=25C, RAMdata:0000h, REV="0", SAP="001", VRN4-0="0", PKP5200="0", PRP12-00="0", VRN4-0=VRP4-0="0" PKP52-00="0", PRP1200="0" -- V mV mV 4.5
0.1 --
5 20 5
ILCD
500
650
5,6
Liquid Crystal Drive Voltage(DDVDH-GND) Output Voltage deviation Variation of average output voltage
VLCD Vo
-- 5
5.5 35
7 8
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HD66787 AC Characteristics (VCC = 1.7 to 3.7 V, Ta = -40 to +85C Note 1) Clock Characteristics (VCC = 1.8 to 3.7 V)
Item External clock frequency External clock duty ratio External clock rise time External clock fall time R-C oscillation clock Symbol fcp Duty trcp tfcp Unit kHz % Test Condition VCC = 1.8 to 3.3 V VCC = 1.8 to 3.3 V Min 100 45 -- Typ 270 50 -- -- 305
Preliminary
Max 600 55 0.2 0.2 366
Notes 9 9 9 9 10
T.B.D.
s VCC = 1.8 to 3.3 V VCC = 1.8 to 3.3 V s -- fOSC kHz Rf = TBD VCC = 3 V Symbol Unit ns ns ns ns ns ns ns ns tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2
244
80-system Bus Interface Timing Characteristics Normal Write Mode (HWM=0) (Vcc = 1.8 to 2.4 V)
Item Bus cycle time Write Read Test Condition Min 600 800 90 350 300 400 -- 0 10 5 60 15 60 15 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- -- -- 200 --
Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time Write (RS to CS*,WR*)
Read (RS to CS*, RD*) Address hold time VLD setup time VLD hold time Write data set up time Write data hold time Read data delay time Read data hold time
T.B.D.
tAH ns Figure 2 Figure 2 tVS ns tVH ns Figure 2 tDSW tH tDDR tDHR ns ns ns ns Figure 2 Figure 2 Figure 2 Figure 2
Rev.0.22, May.23.2003, page 145 of 159
HD66787 High-Speed Write Mode (HWM=1) (Vcc = 1.8 to 2.4 V)
Item Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Write (RS to CS*, WR*) Set up time Read (RS to CS*, RD*) Address hold time VLD setup time VLD hold time Write data set up time Write data hold time Read data delay time Read data hold time Bus cycle time Symbol tCYCW tCYCR PWLW PWLR PWHW PWHR tWRr, WRf tAS Unit ns ns ns ns ns ns ns ns Test Condition Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Min 200 800 90 350 90 400 -- 0 10 5 60 15 60 15 -- 5
Preliminary
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- 25 -- -- -- -- -- -- -- 200 --
T.B.D.
tAH tVS tVH tDSW tH tDDR tDHR ns ns ns ns ns ns ns Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Symbol Unit ns ns ns ns ns ns Test Condition Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 tCYCW tCYCR PWLW PWLR PWHW PWHR
Normal Write Mode (HWM=0) : Vcc = 2.4 to 3.7 V
Item Bus cycle time Write Read Min 250 500 40 250 70 200 -- 0 10 2 25 2 25 2 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- -- -- 200 --
Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Set up time
Write (RS to CS*, WR*)
Read (RS to CS*, WR*)
T.B.D.
tWRr, WRf tAS ns ns Figure 2 Figure 2 tAH tVS tVH tDSW tH tDDR tDHR ns ns ns ns ns ns ns Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2
Address hold time VLD set up time VLD hold time Write data setup time Write data hold time Read data delay time Read data hold time
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HD66787 High-Speed Write Mode (HWM=1) : Vcc = 2.4 to 3.7 V
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high -level pulse width Read high -level pulse width Write/Read rise/fall time Set up time Symbol tCYCW tCYCR PWLw PWLR PWHW PWHR ns ns ns ns Figure 2 Figure 2 Figure 2 Figure 2 Unit ns Test Condition Figure 2 Min 100 500 40 250 40 200 -- 0
Preliminary
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max -- -- -- -- -- -- -- 25 -- -- -- -- -- -- 200 --
Write (RS to CS*, WR*)
Read (RS to CS*, RD*) Address hold time VLD set-up time VLD hold time Write data set up time Write data hold time Read data delay time Read data hold time
T.B.D.
tWRr, WRf ns Figure 2 t WRr, WRf tAH tVS tVH tDSW tH tDDR tDHR ns Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 ns ns ns ns ns ns ns
10 2 25 2 25 2 -- 5
Rev.0.22, May.23.2003, page 147 of 159
HD66787 Serial Peripheral Interface Timing Characteristics Vcc = 1.8 to 2.4 V
Item Symbol Unit Test Condition Min
Preliminary
Typ
Max
Write tSCYC (received) Serial clock cycle time Read (transmitted tSCYC ) Write tSCH (received) Serial clock high-level pulse Read width (transmitted tSCH ) Write tSCL (received) Serial clock low-level pulse Read width (transmitted tSCL ) Serial clock rise/fall time tscr, tscf Chip select set up time tCSU Chip select hold time tCH Serial input data set up time tSISU Serial input data hold time tSIH Serial input data delay time tSOD Serial input data hold time tSOH
us us ns ns
Figure 3 Figure 3 Figure 3 Figure 3
0.1 0.5 40 230 40 230 -- 20 60 30 30 -- 5
-- -- -- -- -- -- -- -- -- -- -- -- --
20 20 -- -- -- -- 20 -- -- -- -- 200 --
T.B.D.
ns ns Figure 3 Figure 3 ns ns ns ns ns ns ns Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3
Symbol Write (receive)) Read (send) Write (receive) Read (send) Write (receive) Read (send) Unit Test Condition
Vcc = 2.4 to 3.3 V
Item Min Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max
tSCYC tSCYC tSCH tSCH tSCL tSCL
us us ns ns
Figure 3 Figure 3 Figure 3 Figure 3
0.1 0.35 40 150 40 150 -- 20 60 30 30 -- 5
20 20 -- -- -- -- 20 -- -- -- -- 130
--
Serial clock cycle time
Serial clock high-level pulse width
Serial clock low-level pulse width Serial clock rise/fall time Chip select set up time Chip select hold time
T.B.D.
ns ns tscr, scf tCSU tCH tSISU tSIH tSOD tSOH ns ns ns ns ns ns ns
Figure 3 Figure 3
Serial input data set up time Serial input data hold time Serial output data delay time Serial output data hold time
Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3
Rev.0.22, May.23.2003, page 148 of 159
HD66787 Reset Timing Characteristics (VCC = 1.8 to 3.7 V)
Item Reset low-level width Reset rise time Symbol tRES trRES Unit ms us Test Condition Figure 4 Figure 4 Min 1 -- Typ -- --
Preliminary
Max -- 10
T.B.D.
Rev.0.22, May.23.2003, page 149 of 159
HD66787 RGB interface timing characteristics 18/16 bit RGB interface (HWM =1), Vcc = 1.8V to 2.4V
Item VSYNC/HSYNC Set up time ENABLE Set up time ENABLE Hold time VLD Set up time VLD Hold time Symbol tSYNCS tENS tENH tVLS tVLH Unit clock ns ns ns ns Test Condition Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 min. 0 20 80 20 80 90 90 200 20 80
Preliminary
typ.
max. 1 25
DOTCLK "Low" Level pulse width
DOTCLK "High" Level pulse width DOTCLK cycle time Data Set up time Data Hole time DOTCLK, VSYNC, HSYNC rising and falling time
T.B.D.
PWDL ns PWDH ns tCYCD tPDS tPDH trgbr, trgbf ns ns ns ns Symbol tSYNCS tENS tENH tVLS tVLH Unit clock ns ns ns ns
Figure 5 Figure 5
Figure 5 Figure 5 Figure 5 Figure 5
18/16 bit RGB interface (HWM = 1), Vcc = 2.4V to 3.7 V
Item VSYNC/HSYNC Set up time ENABLE Set up time ENABLE Hold time VLD Set up time VLD Hold time Test Condition Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 min. 0 10 20 10 40 40 40 100 10 40 typ. max. 1 25
DOTCLK "Low" Level pulse width
DOTCLK "High" Level pulse width DOTCLK cycle time Data Set up time Data Hole time DOTCLK, VSYNC, HSYNC rising and falling time
T.B.D.
PWDL ns Figure 5 PWDH ns Figure 5 tCYCD tPDS tPDH trgbr, trgbf ns ns ns ns Figure 5 Figure 5 Figure 5 Figure 5
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HD66787 6 bit RGB interface (HWM = 1), Vcc = 1.8V to 2.4 V
Item VSYNC/HSYNC Set up time ENABLE Set up time ENABLE Hold time VLD Set up time VLD Hold time DOTCLK "Low" Level pulse width Symbol tSYNCS tENS tENH tVLS Unit clock ns ns ns Test Condition Figure 5 Figure 5 Figure 5 Figure 5 min. 0 20 50 20 65 50 50 120 20 65
Preliminary
typ.
max. 1 25
DOTCLK "High" Level pulse width DOTCLK cycle time Data Set up time Data Hold time DOTCLK, VSYNC, HSYNC rising and falling time
T.B.D.
tVLH ns Figure 5 PWDL ns Figure 5 PWDH ns Figure 5 tCYCD tPDS tPDH trgbr, trgbf ns ns ns ns Figure 5 Figure 5 Figure 5 Figure 5 Symbol tSYNCS tENS tENH tVLS tVLH tVLH Unit clock ns ns ns ns ns Test Condition Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 Figure 5
6 bit RGB interface (HWM = 1), Vcc = 2.4V to 3.3 V
Item VSYNC/HSYNC Set up time ENABLE Set up time ENABLE Hold time VLD Set up time Vcc=2,4 to2,7V VLD Hold time Vcc=2,7 to 3,7V min. 0 10 20 10 40 30 30 30 70 10 40 30 typ. max. 1 25
DOTCLK "Low" Level pulse width DOTCLK "High" Level pulse width DOTCLK cycle time Data Set up time Vcc=2,4 to 2,7V Vcc=2,7 to 3,7V DOTCLK, VSYNC, HSYNC rising and falling time
T.B.D.
PWDL ns Figure 5 PWDH ns Figure 5 tCYCD tPDS tPDH tPDH trgbr, trgbf ns ns ns ns ns Figure 5 Figure 5 Figure 5 Figure 5 Figure 5
Data Hole time
Rev.0.22, May.23.2003, page 151 of 159
HD66787 Liquid crystal driver output characteristics
Item Symbol Unit Test conditions
Vcc=3V, VLCD=5.5V, VDH=5.0V, CR oscillation ;fosc=270kHz(240 lines), Ta=25*A REV="0", SAP="001", *Z VRN4-0="0",VRP4-0="0" PKP52-00="0",PRP12-00="0" PKP52-00="0",PRP12-00="0" All pins changes at the same time from same grayscale. The time till output level reaches *\ 35mV when VCOM polarity changes. Load resistance R=10k*A Load capacity C=20pF
Preliminary
min.
typ.
max.
Note
Driver output delay time
tdd
s
40
(11)
Electrical Characteristics Notes 1. 2.
T.B.D.
Vcc Vcc PMOS NMOS GND PMOS NMOS GND
For bare die and wafer products, specified up to 85C. The following three circuits are I pin, I/O pin, O pin configurations.
Pins: RESET*, CS*, E/WR, RW/RD, RS, OSC1, OPOFF, IM2-1, IM0/ID,TEST
Pins: DB15 -DB2, DB1/SD0, DB0/SD1
T.B.D.
Vcc PMOS
(Input circuit)
NMOS Vcc PMOS
(Tri-state output circuit)
Output enable Output data
NMOS GND
3. 4.
The TEST pin must be grounded and the IM2/1 and IM0/ID pins must be grounded or connected to Vcc. Applies to the resistor value (RSEG) between VSH, GND pins and segment signal pins.
Rev.0.22, May.23.2003, page 152 of 159
T.B.D.
HD66787 5.
Preliminary
This excludes the current flowing through output drive MOSs. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. Even if the CS pin is low or high when an access with the interface pin is not performed, current consumption does not change. The following figure shows the relationship between the operation frequency and current consumption.
Vcc = 3V 440 420 380 360 320 0 100 200 0 300 400 500 600 4.0 4.5 5.0
6.
Vcc = 3V, DDVDH = 5,5V
lop (F)
ILCD (F)
600 400
200
T.B.D.
typ.
( 400
typ.
340
R-C, oscillation frequencies: fosc (kHz)
VDH (V)
7. 8.
This is a voltage difference for the neighboring outputs under the same display condition. The output voltage deviation is a reference value. The fluctuation of average output voltage indicates the difference of average output voltage between chips. The average output voltage is an average voltage within a chip under the same display condition. Applies to the case when clocks are supplied internally (figure).
9.
T.B.D.
Th Tl OSC1 0.7Vcc 0.5Vcc 0.3Vcc OSC2 trcp t fcp
2k
Oscillator
T.B.D.
Duty =
Th Th + Tl x 100%
Open
10. Applies to the internal oscillator operations using external oscillation resistor Rf (figure and table).
Rev.0.22, May.23.2003, page 153 of 159
HD66787
Preliminary
OSC1 Rf
OSC2
T.B.D.
Vcc = 2 V 333 258 222 203 Vcc = 2.4 V 372 284 243 222 401 305 258 235
The oscillation frequency may vary depending on the capacitors for OSC1, OSC2 pins. Place OSC1 and OSC2 close to each other.
External Resistance Value and R-C Oscillation Frequency (Referential Data)
External Resistance (Rf) 110 k 150 k 180 k 200 k 240 k 270 k 300 k 390 k 430 k Vcc = 1.8 V 299 234 202 186 R-C Oscillation Frequency: fosc Vcc = 3 V Vcc = 3.3 V 411 311 263 240 202 181 163 128 116
T.B.D.
160 145 173 157
188 169
198 177
132 106 97
143 113
153 121
161 126
104
110
115
11. Applies to the internal oscillator operations using external oscillation resistor Rf (figure and table).
Reference data 70 60 50 40 30 20 10
tDD (S)
LCD driver output delay time
T.B.D.
10 20 30 Load Capacity C(pF)
Vcc =3V, VLCD = 5.5V, VDH = 5.0V, R-C Oscillation; fosc = 270kHz (240line), Ta = 25 Centigrade, REV = "0", SAP ="001", VRN4-0 = "0", VRP4-0 = "0", PKP52-00 = "0", PRP12-00 ="0", PKN52-00 = "0", PRN12-00 ="0", All pins chnge at the same time from same grayscale. The time till output level reaches +/-35mV when VCOM polarity changes. Load resistance R = 10k/pin
Rev.0.22, May.23.2003, page 154 of 159
HD66787 Load circuits for measuring AC characteristics
Preliminary
AC characteristic measuring load circuit Data bus : DB17-DB0, PD17-0 Test Point
T.B.D.
LCD output : S1- S528 Test Point 50pF Lord Resistance R 10k
LCD driver output characteristic measuring load circuit
Lord Capacity C 20pF
80-system Bus Operation
RS
VIH VIL
tAS
VIH VIL
tAH
CS*
WR* RD*
T.B.D.
VIL
Note 1) PWLW, PWLR
VIH
PWHW, PWHR
VIL
VIH VIL
VIH
tWRr
tCYCW, tCYCR
tWRf
tDSW DB0 to DB1 5
tDDR
tHWR VIH VIL
tDHR
VIH VIL
Wrire data
DB0 to DB1 5
VOH1 VOL1 Read data
VOH1 VOL1
Note 1) PWLW and PWLR is specified in the overlapped period when CS* is low and WR* or RD* is low. Note 2) Parallel data transfer is enabled on the DB15-8 pins when the 8-bit bus interface is used. Fix the DB7-0 pins to Vcc or GND.
Rev.0.22, May.23.2003, page 155 of 159
HD66787 Clock Synchronized Serial Interface Operation
Start: S
Preliminary
End : P VIH VIL tSCYC tscf tSCH tSCL tCH VIH VIH VIH
CS*
VIL
tCSU
tscr
SCL
VIH
VIL
SDI
T.B.D.
VIL VIL VIL tSISU tSIH VIH VIL Input data VIH VIL Input data tSOD tSOH VOH1 VOL1 VOH1 VOL1 Output data Output data
SDO
RESET Operation
RESET *
VIL
T.B.D.
tRES
trRE S
VIL VIL
Rev.0.22, May.23.2003, page 156 of 159
HD66787 RGB I/F Operation
trgbf trgbf VIH VIL VIH VIL tENS ENABLE VIH VIH VIL tENH VIH VIL VIH VIL
Preliminary
tSYNCS
VSYNC HSYNC
VLD
T.B.D.
VIL tVLS tVLH VIH VIL VIH VIL VIH VIL VIH VIL trgbf trgbf PWDL VIH VIL VIL PWDH VIH VIL VIH tPDS tPDH VIH VIL VIH VIL VIH VIL VIH VIL Write Data
DOTCLK
PD17-0
Liquid Crystal Driver Output
VCOM
S1-528
T.B.D.
tPDS Ce rta in g ray s ca le v o l t a g e +/-35mV Certain grayscale voltage +/-35mV
Rev.0.22, May.23.2003, page 157 of 159
HD66787
Preliminary
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
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Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.0.22, May.23.2003, page 158 of 159
HD66787
Preliminary
Revision Record
Rev. 0.1 Date 2003.05.08 Contents of Modification First issue Drawn by Approved by
Rev.0.22, May.23.2003, page 159 of 159

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